From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 13 Mar 2021 13:57:24 +0000 (+0000)
Subject: expand SVi to 8 bits
X-Git-Tag: convert-csv-opcode-to-binary~31
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=896f973c9d98d0ec0ffd80f3a4d509443f56940f;p=libreriscv.git

expand SVi to 8 bits
---

diff --git a/openpower/isa/simplev.mdwn b/openpower/isa/simplev.mdwn
index cada3b6ae..d283db966 100644
--- a/openpower/isa/simplev.mdwn
+++ b/openpower/isa/simplev.mdwn
@@ -10,13 +10,13 @@ Pseudo-code:
     VLimm <- SVi + 1
     if vs = 1 then
         if RA = 0 then
-            VL <- (RA)
+            VL <- (RA)[57:63]
         else
-            VL <- VLimm
+            VL <- VLimm[2:8]
     else
         VL <- SVSTATE[7:13]
     if ms = 1 then
-        MVL <- VLimm
+        MVL <- VLimm[2:8]
     else
         MVL <- SVSTATE[0:6]
     if VL > MVL then
@@ -24,7 +24,7 @@ Pseudo-code:
     SVSTATE[0:6] = MVL
     SVSTATE[7:13] = VL
     if RT != 0 then
-        RT <- VL
+        RT <- VL || [0] * 58
 
 Special Registers Altered:
 
diff --git a/openpower/isatables/fields.text b/openpower/isatables/fields.text
index ea4f461e0..c0bccb353 100644
--- a/openpower/isatables/fields.text
+++ b/openpower/isatables/fields.text
@@ -709,7 +709,7 @@
          Field used by the Segment Register Manipulation
          instructions (see Book III).
          Formats: X
-    SVi (16:21)
+    SVi (16:23)
          Simple-V immediate field for setting VL or MVL
          Formats: SVL
     SX,S (28,6:10)