From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 10 Sep 2022 15:12:07 +0000 (+0100)
Subject: SVP64-Single para
X-Git-Tag: opf_rfc_ls005_v1~513
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=898333529f61f7bd6941a6a9a0d49b9e79d1f017;p=libreriscv.git

SVP64-Single para
---

diff --git a/openpower/sv/rfc/ls001.mdwn b/openpower/sv/rfc/ls001.mdwn
index 5556e2701..755951aa1 100644
--- a/openpower/sv/rfc/ls001.mdwn
+++ b/openpower/sv/rfc/ls001.mdwn
@@ -190,6 +190,15 @@ The primary options are:
   be saturated (without adding explicit scalar saturated opcodes)
 * Reduction and Prefix-Sum (Fibonnacci Series) Modes
 
+The `SVP64-Single` 24-bit encoding focusses primarily on ensuring that
+all 128 Scalar registers are fully accessible, provides element-width
+overrides, one-bit predication
+and brings Saturation to all existing Scalar operations.
+BF16 and FP16 are thus
+provided in the Scalar Power ISA without one single explicit FP16 or BF16
+32-bit opcode being added.  The downside: such Scalar operations are
+all 64-bit encodings.
+
 \newpage{}
 # Simple-V REMAP subsystem