From: Luke Kenneth Casson Leighton Date: Fri, 28 May 2021 17:45:40 +0000 (+0100) Subject: add SVP64 RM LDST mode enum X-Git-Tag: xlen-bcd~511 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=898bb1687d1f2703d93ba7855a02cc531a370f0f;p=openpower-isa.git add SVP64 RM LDST mode enum --- diff --git a/src/openpower/decoder/power_enums.py b/src/openpower/decoder/power_enums.py index 0f0e7490..429a1684 100644 --- a/src/openpower/decoder/power_enums.py +++ b/src/openpower/decoder/power_enums.py @@ -206,6 +206,12 @@ class SVP64sat(Enum): SIGNED = 1 UNSIGNED = 2 +@unique +class SVP64LDSTmode(Enum): + NORMAL = 0 + ELSTRIDE = 1 + UNITSTRIDE = 2 + # supported instructions: make sure to keep up-to-date with CSV files # just like everything else diff --git a/src/openpower/decoder/power_svp64_rm.py b/src/openpower/decoder/power_svp64_rm.py index 981e51a8..d1d65e30 100644 --- a/src/openpower/decoder/power_svp64_rm.py +++ b/src/openpower/decoder/power_svp64_rm.py @@ -41,7 +41,7 @@ https://libre-soc.org/openpower/sv/svp64/ https://libre-soc.org/openpower/sv/ldst/ LD/ST immed: -00 str sz dz normal mode +00 els sz dz normal mode 01 inv CR-bit Rc=1: ffirst CR sel 01 inv els RC1 Rc=0: ffirst z/nonz 10 N dz els sat mode: N=0/1 u/s