From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 18 Jun 2020 10:26:35 +0000 (+0100)
Subject: debugging test_issuer.py general test cases
X-Git-Tag: div_pipeline~329^2~3
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=89a1816ae022d09ed5d08ad6f83f868a06dc40e5;p=soc.git

debugging test_issuer.py general test cases
---

diff --git a/src/soc/simple/test/test_issuer.py b/src/soc/simple/test/test_issuer.py
index b3a50c0a..953525e3 100644
--- a/src/soc/simple/test/test_issuer.py
+++ b/src/soc/simple/test/test_issuer.py
@@ -30,6 +30,7 @@ from soc.fu.shift_rot.test.test_pipe_caller import ShiftRotTestCase
 from soc.fu.cr.test.test_pipe_caller import CRTestCase
 from soc.fu.branch.test.test_pipe_caller import BranchTestCase
 from soc.fu.ldst.test.test_pipe_caller import LDSTTestCase
+from soc.simulator.test_sim import GeneralTestCases
 
 
 def setup_i_memory(imem, startaddr, instructions):
@@ -74,9 +75,15 @@ class TestRunner(FHDLTestCase):
                 print(test.name)
                 program = test.program
                 self.subTest(test.name)
+                print ("regs", test.regs)
+                print ("sprs", test.sprs)
+                print ("cr", test.cr)
+                print ("mem", test.mem)
+                print ("msr", test.msr)
+                print ("assem", program.assembly)
                 sim = ISA(pdecode2, test.regs, test.sprs, test.cr, test.mem,
                           test.msr)
-                gen = program.generate_instructions()
+                gen = list(program.generate_instructions())
                 instructions = list(zip(gen, program.assembly.splitlines()))
 
                 pc = 0 # start address
@@ -126,6 +133,7 @@ class TestRunner(FHDLTestCase):
 if __name__ == "__main__":
     unittest.main(exit=False)
     suite = unittest.TestSuite()
+    #suite.addTest(TestRunner(GeneralTestCases.test_data))
     suite.addTest(TestRunner(LDSTTestCase.test_data))
     suite.addTest(TestRunner(CRTestCase.test_data))
     suite.addTest(TestRunner(ShiftRotTestCase.test_data))
diff --git a/src/soc/simulator/test_sim.py b/src/soc/simulator/test_sim.py
index 78afefaa..9ab807d6 100644
--- a/src/soc/simulator/test_sim.py
+++ b/src/soc/simulator/test_sim.py
@@ -201,6 +201,7 @@ class GeneralTestCases(FHDLTestCase):
 
     def run_tst_program(self, prog, initial_regs=None, initial_sprs=None,
                                     initial_mem=None):
+        initial_regs = [0] * 32
         tc = TestCase(prog, self.test_name, initial_regs, initial_sprs, 0,
                                             initial_mem, 0)
         self.test_data.append(tc)