From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 2 Oct 2021 17:14:11 +0000 (+0100)
Subject: add bool PartitionedSignal test
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=89db3381756fc618146436a7dd0ad5572e9d61f4;p=ieee754fpu.git

add bool PartitionedSignal test
---

diff --git a/src/ieee754/part/partsig.py b/src/ieee754/part/partsig.py
index 24502b2f..79cc6c34 100644
--- a/src/ieee754/part/partsig.py
+++ b/src/ieee754/part/partsig.py
@@ -19,6 +19,7 @@ nmigen.Case, or other constructs: only Mux and other logic.
 from ieee754.part_mul_add.adder import PartitionedAdder
 from ieee754.part_cmp.eq_gt_ge import PartitionedEqGtGe
 from ieee754.part_bits.xor import PartitionedXOR
+from ieee754.part_bits.bool import PartitionedBool
 from ieee754.part_shift.part_shift_dynamic import PartitionedDynamicShift
 from ieee754.part_shift.part_shift_scalar import PartitionedScalarShift
 from ieee754.part_mul_add.partpoints import make_partition2, PartitionPoints
@@ -49,7 +50,7 @@ global modnames
 modnames = {}
 # for sub-modules to be created on-demand. Mux is done slightly
 # differently (has its own global)
-for name in ['add', 'eq', 'gt', 'ge', 'ls', 'xor']:
+for name in ['add', 'eq', 'gt', 'ge', 'ls', 'xor', 'bool']:
     modnames[name] = 0
 
 
@@ -329,8 +330,11 @@ class PartitionedSignal(UserValue):
         Value, out
             ``1`` if any bits are set, ``0`` otherwise.
         """
-        return self.any() # have to see how this goes
-        #return Operator("b", [self])
+        width = len(self.sig)
+        pa = PartitionedBool(width, self.partpoints)
+        setattr(self.m.submodules, self.get_modname("bool"), pa)
+        self.m.d.comb += pa.a.eq(self.sig)
+        return pa.output
 
     def any(self):
         """Check if any bits are ``1``.
diff --git a/src/ieee754/part/test/test_partsig.py b/src/ieee754/part/test/test_partsig.py
index a1eb452e..6937b07e 100644
--- a/src/ieee754/part/test/test_partsig.py
+++ b/src/ieee754/part/test/test_partsig.py
@@ -203,6 +203,7 @@ class TestAddMod(Elaboratable):
         self.sub_carry_out = Signal(len(partpoints)+1)
         self.neg_output = Signal(width)
         self.xor_output = Signal(len(partpoints)+1)
+        self.bool_output = Signal(len(partpoints)+1)
 
     def elaborate(self, platform):
         m = Module()
@@ -231,6 +232,7 @@ class TestAddMod(Elaboratable):
         comb += self.neg_output.eq((-self.a).sig)
         # horizontal operators
         comb += self.xor_output.eq(self.a.xor())
+        comb += self.bool_output.eq(self.a.bool())
         # left shift
         comb += self.ls_output.eq(self.a << self.b)
         # right shift
@@ -577,6 +579,15 @@ class TestPartitionedSignal(unittest.TestCase):
                     test >>= 1
                 return result
 
+            def test_bool_fn(a, mask):
+                test = (a & mask)
+                result = 0
+                while test != 0:
+                    bit = (test & 1)
+                    result |= bit
+                    test >>= 1
+                return result
+
             def test_horizop(msg_prefix, test_fn, mod_attr, *maskbit_list):
                 randomvals = []
                 for i in range(10):
@@ -612,6 +623,7 @@ class TestPartitionedSignal(unittest.TestCase):
                     self.assertEqual(y, outval, msg % str(maskbit_list))
 
             for (test_fn, mod_attr) in ((test_xor_fn, "xor"),
+                                        (test_bool_fn, "bool"),
                                         #(test_ne_fn, "ne"),
                                         ):
                 yield part_mask.eq(0)