From: Rick Altherr <kc8apf@kc8apf.net>
Date: Sun, 31 Jan 2016 03:43:29 +0000 (-0800)
Subject: rtlil: improve performance of SigSpec::replace(SigSpec, SigSpec, SigSpec*)
X-Git-Tag: yosys-0.6~30^2~2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=89dc40f162a7f06d15ad489066dd0cc64937fbd7;p=yosys.git

rtlil: improve performance of SigSpec::replace(SigSpec, SigSpec, SigSpec*)
---

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 91b737151..ca4480576 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -2584,18 +2584,26 @@ void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec
 
 void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with, RTLIL::SigSpec *other) const
 {
+	log_assert(other != NULL);
+	log_assert(width_ == other->width_);
 	log_assert(pattern.width_ == with.width_);
 
 	pattern.unpack();
 	with.unpack();
+	unpack();
+	other->unpack();
 
-	dict<RTLIL::SigBit, RTLIL::SigBit> rules;
-
-	for (int i = 0; i < GetSize(pattern.bits_); i++)
-		if (pattern.bits_[i].wire != NULL)
-			rules[pattern.bits_[i]] = with.bits_[i];
+	for (int i = 0; i < GetSize(pattern.bits_); i++) {
+		if (pattern.bits_[i].wire != NULL) {
+			for (int j = 0; j < GetSize(bits_); j++) {
+				if (bits_[j] == pattern.bits_[i]) {
+					other->bits_[j] = with.bits_[i];
+				}
+			}
+		}
+	}
 
-	replace(rules, other);
+	other->check();
 }
 
 void RTLIL::SigSpec::replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules)