From: lkcl <lkcl@web>
Date: Wed, 1 Sep 2021 19:45:43 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~261
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=89e8d463b6902a25bf19a5884f5f00b719d9ef38;p=libreriscv.git

---

diff --git a/openpower/sv/ldst.mdwn b/openpower/sv/ldst.mdwn
index 51dafd692..9037dc04e 100644
--- a/openpower/sv/ldst.mdwn
+++ b/openpower/sv/ldst.mdwn
@@ -212,10 +212,10 @@ A summary of the effect of Vectorisation of src or dest:
      imm(RA)  RT.s   RA.v   no stride allowed
      imm(RA)  RT.v   RA.s   stride-select allowed
      imm(RA)  RT.s   RA.s   not vectorised
-     RA,RB    RT.v  RA/RB.v ffirst banned
-     RA,RB    RT.s  RA/RB.v ffirst banned
-     RA,RB    RT.v  RA/RB.s VSPLAT possible
-     RA,RB    RT.s  RA/RB.s not vectorised
+     RA,RB    RT.v  {RA|RB}.v ffirst banned
+     RA,RB    RT.s  {RA|RB}.v ffirst banned
+     RA,RB    RT.v  {RA&RB}.s VSPLAT possible
+     RA,RB    RT.s  {RA&RB}.s not vectorised
 
 Signed Effective Address computation is only relevant for
 Vector Indexed Mode, when elwidth overrides are applied.