From: lkcl <lkcl@web>
Date: Wed, 5 Oct 2022 03:04:43 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~178
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=89eb4cd6458000dab671fc5921f2b0d8eed6702e;p=libreriscv.git

---

diff --git a/openpower/sv/svp64/discussion.mdwn b/openpower/sv/svp64/discussion.mdwn
index c996d3930..78e782c28 100644
--- a/openpower/sv/svp64/discussion.mdwn
+++ b/openpower/sv/svp64/discussion.mdwn
@@ -4,7 +4,6 @@ the original assessment for SVP from 18 months ago concluded that it should be e
 
 question: has anything changed about the assessment that was done, which concluded that for scalar SVP regs they should overlap completely with scalar ISA regs?
 
-
 # Notes on requirements for bit allocations
 
 do not try to jam VL or MAXVL in.  go with the flow of 24 bits spare.
@@ -230,6 +229,14 @@ Summary so far:
   bit for auto-VL=1.  requires an extra reduction instruction.
 * sv.branches should not be touched. at all.
 
+## only 1 src/dest
+
+Instructions in this category are usually Unvectoriseable
+or they are Load-Immediates. `fmvis` for example, is 1-Write,
+whilst SV.Branch-Conditional is BI (CR field bit).
+
+TBD
+
 ## answers to 2, RM Modes
 
 **Normal Mode:**