From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Tue, 17 Mar 2015 15:22:22 +0000 (+0100)
Subject: genlib/io: add optional external rst to CRG
X-Git-Tag: 24jan2021_ls180~2099^2~168
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=89fefef3f8fc78b1fceefe93dcb3385efacdb79a;p=litex.git

genlib/io: add optional external rst to CRG
---

diff --git a/migen/genlib/io.py b/migen/genlib/io.py
index 586dcf8c..cd436072 100644
--- a/migen/genlib/io.py
+++ b/migen/genlib/io.py
@@ -35,7 +35,7 @@ class DifferentialOutput(Special):
 		raise NotImplementedError("Attempted to use a differential output, but platform does not support them")
 
 class CRG(Module):
-	def __init__(self, clk):
+	def __init__(self, clk, rst=Signal()):
 		self.clock_domains.cd_sys = ClockDomain()
 		self.clock_domains.cd_por = ClockDomain(reset_less=True)
 
@@ -46,7 +46,7 @@ class CRG(Module):
 
 		# Power on Reset (vendor agnostic)
 		rst_n = Signal()
-		self.sync.por += rst_n.eq(1)
+		self.sync.por += rst_n.eq(1 & ~rst)
 		self.comb += [
 			self.cd_sys.clk.eq(clk),
 			self.cd_por.clk.eq(clk),