From: Naveen.H.S <naveenh@kpitcummins.com>
Date: Wed, 12 Jul 2006 22:31:32 +0000 (+0000)
Subject: muldiv.md (umulhisi3_c): Use only registers for dest.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8a01e7d967e072a6eca0106c6e31696f58ca771f;p=gcc.git

muldiv.md (umulhisi3_c): Use only registers for dest.

* config/m32c/muldiv.md (umulhisi3_c): Use only registers for
dest.
(umulhisi3_r): Likewise.

From-SVN: r115400
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 0f97b43b517..0ba96f7cb3c 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2006-07-12  Naveen.H.S  <naveenh@kpitcummins.com>
+
+	* config/m32c/muldiv.md (umulhisi3_c): Use only registers for 
+	dest.
+	(umulhisi3_r): Likewise.
+
 2006-07-12  Paolo Carlini  <pcarlini@suse.de>
 
 	PR libstdc++/27878
diff --git a/gcc/config/m32c/muldiv.md b/gcc/config/m32c/muldiv.md
index 9313088b552..6913ea9a729 100644
--- a/gcc/config/m32c/muldiv.md
+++ b/gcc/config/m32c/muldiv.md
@@ -107,18 +107,18 @@
 )
 
 (define_insn "umulhisi3_c"
-  [(set (match_operand:SI 0 "mra_operand" "=RsiSd,??Rmm")
-        (mult:SI (zero_extend:SI (match_operand:HI 1 "mra_operand" "%0,0"))
-                 (match_operand 2 "immediate_operand" "i,i")))]
+  [(set (match_operand:SI 0 "ra_operand" "=Rsi")
+        (mult:SI (zero_extend:SI (match_operand:HI 1 "mra_operand" "%0"))
+                 (match_operand 2 "immediate_operand" "i")))]
   ""
   "mulu.w\t%u2,%1"
   [(set_attr "flags" "o")]
 )
 
 (define_insn "umulhisi3_r"
-  [(set (match_operand:SI 0 "mra_operand" "=RsiSd,RsiSd,??Rmm,??Rmm")
-        (mult:SI (zero_extend:SI (match_operand:HI 1 "mra_operand" "%0,0,0,0"))
-                 (zero_extend:SI (match_operand:HI 2 "mra_operand" "RhiSd,?Rmm,RhiSd,?Rmm"))))]
+  [(set (match_operand:SI 0 "mra_operand" "=Rsi,Rsi")
+        (mult:SI (zero_extend:SI (match_operand:HI 1 "mra_operand" "%0,0"))
+                 (zero_extend:SI (match_operand:HI 2 "mra_operand" "RhiSd,?Rmm"))))]
   ""
   "mulu.w\t%u2,%1"
   [(set_attr "flags" "o")]