From: Segher Boessenkool <segher@kernel.crashing.org>
Date: Fri, 5 Sep 2014 19:17:08 +0000 (+0200)
Subject: re PR target/63187 (Unrecognizable insn ICE due to revision 214080)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8a03df77b1b29bc1a1609a68d694890a28e089a4;p=gcc.git

re PR target/63187 (Unrecognizable insn ICE due to revision 214080)

2014-09-05  Segher Boessenkool  <segher@kernel.crashing.org>

	PR target/63187
	* config/rs6000/rs6000.md (*and<mode>3_imm_dot, *and<mode>3_imm_dot2):
	Do not allow any_mask_operand for operands[2].
	(*and<mode>3_imm_mask_dot, *and<mode>3_imm_mask_dot2): New.

From-SVN: r214976
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index dd767585ef6..18951b3b47e 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@
+2014-09-05  Segher Boessenkool  <segher@kernel.crashing.org>
+
+	PR target/63187
+	* config/rs6000/rs6000.md (*and<mode>3_imm_dot, *and<mode>3_imm_dot2):
+	Do not allow any_mask_operand for operands[2].
+	(*and<mode>3_imm_mask_dot, *and<mode>3_imm_mask_dot2): New.
+
 2014-09-05  David Malcolm  <dmalcolm@redhat.com>
 
 	* config/arc/arc.c (arc_print_operand): Use insn method of
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 8f3549ebdd8..2df8e4193fd 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -2736,7 +2736,8 @@
    (clobber (match_scratch:GPR 0 "=r,r"))
    (clobber (match_scratch:CC 4 "=X,x"))]
   "(<MODE>mode == Pmode || UINTVAL (operands[2]) <= 0x7fffffff)
-   && rs6000_gen_cell_microcode"
+   && rs6000_gen_cell_microcode
+   && !any_mask_operand (operands[2], <MODE>mode)"
   "@
    andi%e2. %0,%1,%u2
    #"
@@ -2763,7 +2764,8 @@
 		 (match_dup 2)))
    (clobber (match_scratch:CC 4 "=X,x"))]
   "(<MODE>mode == Pmode || UINTVAL (operands[2]) <= 0x7fffffff)
-   && rs6000_gen_cell_microcode"
+   && rs6000_gen_cell_microcode
+   && !any_mask_operand (operands[2], <MODE>mode)"
   "@
    andi%e2. %0,%1,%u2
    #"
@@ -2780,6 +2782,56 @@
    (set_attr "dot" "yes")
    (set_attr "length" "4,8")])
 
+(define_insn_and_split "*and<mode>3_imm_mask_dot"
+  [(set (match_operand:CC 3 "cc_reg_operand" "=x,??y")
+	(compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,r")
+			     (match_operand:GPR 2 "logical_const_operand" "n,n"))
+		    (const_int 0)))
+   (clobber (match_scratch:GPR 0 "=r,r"))]
+  "(<MODE>mode == Pmode || UINTVAL (operands[2]) <= 0x7fffffff)
+   && rs6000_gen_cell_microcode
+   && any_mask_operand (operands[2], <MODE>mode)"
+  "@
+   andi%e2. %0,%1,%u2
+   #"
+  "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
+  [(set (match_dup 0)
+	(and:GPR (match_dup 1)
+		 (match_dup 2)))
+   (set (match_dup 3)
+	(compare:CC (match_dup 0)
+		    (const_int 0)))]
+  ""
+  [(set_attr "type" "logical")
+   (set_attr "dot" "yes")
+   (set_attr "length" "4,8")])
+
+(define_insn_and_split "*and<mode>3_imm_mask_dot2"
+  [(set (match_operand:CC 3 "cc_reg_operand" "=x,??y")
+	(compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,r")
+			     (match_operand:GPR 2 "logical_const_operand" "n,n"))
+		    (const_int 0)))
+   (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
+	(and:GPR (match_dup 1)
+		 (match_dup 2)))]
+  "(<MODE>mode == Pmode || UINTVAL (operands[2]) <= 0x7fffffff)
+   && rs6000_gen_cell_microcode
+   && any_mask_operand (operands[2], <MODE>mode)"
+  "@
+   andi%e2. %0,%1,%u2
+   #"
+  "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
+  [(set (match_dup 0)
+	(and:GPR (match_dup 1)
+		 (match_dup 2)))
+   (set (match_dup 3)
+	(compare:CC (match_dup 0)
+		    (const_int 0)))]
+  ""
+  [(set_attr "type" "logical")
+   (set_attr "dot" "yes")
+   (set_attr "length" "4,8")])
+
 
 (define_insn "*and<mode>3_mask"
   [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")