From: Dmitry Selyutin <ghostmansd@gmail.com>
Date: Tue, 2 Aug 2022 18:27:42 +0000 (+0300)
Subject: power_enums: introduce SVExtraReg enum
X-Git-Tag: sv_maxu_works-initial~149
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8a078878381d0078c9f62c5470bb35bd55900f0b;p=openpower-isa.git

power_enums: introduce SVExtraReg enum
---

diff --git a/src/openpower/decoder/power_enums.py b/src/openpower/decoder/power_enums.py
index 723fbc5c..d175c2f1 100644
--- a/src/openpower/decoder/power_enums.py
+++ b/src/openpower/decoder/power_enums.py
@@ -15,6 +15,7 @@ get_spr_enum
 """
 
 from enum import (
+    auto,
     Enum as _Enum,
     unique,
 )
@@ -209,6 +210,35 @@ class SVExtraRegType(Enum):
     DST = 'd'
 
 
+class SVExtraReg(Enum):
+    NONE = auto()
+    RA = auto()
+    RA_OR_ZERO = RA
+    RB = auto()
+    RC = auto()
+    RS = auto()
+    RT = auto()
+    RT_OR_ZERO = RT
+    FRA = auto()
+    FRB = auto()
+    FRC = auto()
+    FRS = auto()
+    FRT = auto()
+    CR = auto()
+    CR0 = auto()
+    CR1 = auto()
+    BF = auto()
+    BFA = auto()
+    BA = auto()
+    BB = auto()
+    BC = auto()
+    BI = auto()
+    BT = auto()
+    BFT = auto()
+    WHOLE_REG = auto()
+    SPR = auto()
+
+
 @unique
 class SVP64PredMode(Enum):
     ALWAYS = 0