From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 4 Jun 2018 02:15:13 +0000 (+0100)
Subject: clarify
X-Git-Tag: convert-csv-opcode-to-binary~5294
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8a07e615c67f2551632c7982097aed28d8fcae54;p=libreriscv.git

clarify
---

diff --git a/simple_v_extension/simple_v_chennai_2018.tex b/simple_v_extension/simple_v_chennai_2018.tex
index 892475219..7cd08ad85 100644
--- a/simple_v_extension/simple_v_chennai_2018.tex
+++ b/simple_v_extension/simple_v_chennai_2018.tex
@@ -486,14 +486,16 @@ for (i = 0; i < 16; i++) // 16 CSRs?
 \frame{\frametitle{What's the downside(s) of SV?}
  \begin{itemize}
    \item EVERY register operation is inherently parallelised\\
-	     (scalar ops are just vectors of length 1)\vspace{8pt}
+	     (scalar ops are just vectors of length 1)\vspace{4pt}
    \item An extra pipeline phase is pretty much essential\\
-         for fast low-latency implementations\vspace{8pt}
+         for fast low-latency implementations\vspace{4pt}
    \item Assuming an instruction FIFO, N ops could be taken off\\
          of a parallel op per cycle (avoids filling entire FIFO;\\
-         also is less work per cycle: lower complexity / latency)\vspace{8pt}
+         also is less work per cycle: lower complexity / latency)\vspace{4pt}
    \item With zeroing off, skipping non-predicated elements is hard:\\
-         it is however an optimisation (and could be skipped).
+         it is however an optimisation (and could be skipped).\vspace{4pt}
+   \item Setting up the tables (interpreting the CSR key-value stores)\\
+	     might be a bit complex to optimise.
   \end{itemize}
 }