From: Staf Verhaegen Date: Mon, 16 Mar 2020 08:53:38 +0000 (+0100) Subject: Re: [libre-riscv-dev] LibreSOC - RISCV and POWER dual architecture feasibility X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8a090ae31655192df578c433bd30cf8d6a0e798b;p=libre-riscv-dev.git Re: [libre-riscv-dev] LibreSOC - RISCV and POWER dual architecture feasibility --- diff --git a/37/0e4651bc080eb2ce3172e445317ead364451ad b/37/0e4651bc080eb2ce3172e445317ead364451ad new file mode 100644 index 0000000..837f464 --- /dev/null +++ b/37/0e4651bc080eb2ce3172e445317ead364451ad @@ -0,0 +1,105 @@ +Return-path: +Envelope-to: publicinbox@libre-riscv.org +Delivery-date: Mon, 16 Mar 2020 08:53:52 +0000 +Received: from localhost ([::1] helo=libre-riscv.org) + by libre-riscv.org with esmtp (Exim 4.89) + (envelope-from ) + id 1jDlVP-0007TE-Kg; Mon, 16 Mar 2020 08:53:51 +0000 +Received: from vps2.stafverhaegen.be ([85.10.201.15]) + by libre-riscv.org with esmtp (Exim 4.89) + (envelope-from ) id 1jDlVO-0007T8-AF + for libre-riscv-dev@lists.libre-riscv.org; Mon, 16 Mar 2020 08:53:50 +0000 +Received: from hpdc7800 (hpdc7800 [10.0.0.1]) + by vps2.stafverhaegen.be (Postfix) with ESMTP id 7BDD911C03F5 + for ; + Mon, 16 Mar 2020 09:53:49 +0100 (CET) +Message-ID: +From: Staf Verhaegen +To: libre-riscv-dev@lists.libre-riscv.org +Date: Mon, 16 Mar 2020 09:53:38 +0100 +In-Reply-To: <20200316091420.15087a26fab1be3d5fc23953@gmx.com> +References: <6AC4EFD4-AA30-42C7-855A-CE68A62F107F@gatech.edu> + + <20200315051018.svaw4aor7ifwn725@topoi.pooq.com> + + + + <1BB9EA49-275B-4365-963E-9FC21D574BB7@gatech.edu> + <16F24775-E25B-4E31-A1D4-145EB65FB1D8@gatech.edu> + + <75CA4609-370F-455E-A88D-50E3766D45D7@gatech.edu> + + <884F8FEE-60FF-4580-A2E7-8AAA40A6DB6B@gatech.edu> + + <20200316091420.15087a26fab1be3d5fc23953@gmx.com> +Organization: FibraServi bvba +X-Mailer: Evolution 3.28.5 (3.28.5-5.el7) +Mime-Version: 1.0 +X-Content-Filtered-By: Mailman/MimeDel 2.1.23 +Subject: Re: [libre-riscv-dev] LibreSOC - RISCV and POWER dual architecture + feasibility +X-BeenThere: libre-riscv-dev@lists.libre-riscv.org +X-Mailman-Version: 2.1.23 +Precedence: list +List-Id: Libre-RISCV General Development + +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Reply-To: Libre-RISCV General Development + +Content-Type: multipart/mixed; boundary="===============1146271254020598867==" +Errors-To: libre-riscv-dev-bounces@lists.libre-riscv.org +Sender: "libre-riscv-dev" + + +--===============1146271254020598867== +Content-Type: multipart/signed; micalg="pgp-sha1"; protocol="application/pgp-signature"; + boundary="=-VUv/2dhqEWvnYk3AaT6b" + + +--=-VUv/2dhqEWvnYk3AaT6b +Content-Type: text/plain; charset="UTF-8" +Content-Transfer-Encoding: quoted-printable + +Lauri Kasanen schreef op ma 16-03-2020 om 09:14 [+0200]: +> On Sun, 15 Mar 2020 12:43:45 -0700Jacob Lifshay wrote: +> > Later (for Libre-SOC v2 or v3), it might be a good idea to add support = +forx86 and x86_64 user-mode since the patents for the base ISA will haveexp= +ired by then. This would help give us an advantage since it would allowus t= +o run legacy software. +>=20 +> 486 and 586 patents had expired years ago, and we had Chinese 1 GHzimplem= +entations of those (vortex86). Now they have 686 models, so Itake pentium p= +ro patents are also up for use. + +I think these were because Via had cross-patent license agreement with Inte= +l. + +greets, +Staf. + + +--=-VUv/2dhqEWvnYk3AaT6b-- + + + +--===============1146271254020598867== +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: base64 +Content-Disposition: inline + +X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KbGlicmUtcmlz +Y3YtZGV2IG1haWxpbmcgbGlzdApsaWJyZS1yaXNjdi1kZXZAbGlzdHMubGlicmUtcmlzY3Yub3Jn +Cmh0dHA6Ly9saXN0cy5saWJyZS1yaXNjdi5vcmcvbWFpbG1hbi9saXN0aW5mby9saWJyZS1yaXNj +di1kZXYK + +--===============1146271254020598867==-- + +