From: Tim Newsome <tim@sifive.com>
Date: Fri, 10 Feb 2017 19:31:30 +0000 (-0800)
Subject: Implement hartstatus field.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8a09a059dc3ddd0b6df8028ae7e4c9e6e1c9d41e;p=riscv-isa-sim.git

Implement hartstatus field.
---

diff --git a/riscv/debug_module.cc b/riscv/debug_module.cc
index e5811be..ba30603 100644
--- a/riscv/debug_module.cc
+++ b/riscv/debug_module.cc
@@ -12,7 +12,8 @@
 #  define D(x)
 #endif
 
-debug_module_t::debug_module_t() :
+debug_module_t::debug_module_t(sim_t *sim) :
+  sim(sim),
   dmcontrol(1 << DMI_DMCONTROL_VERSION_OFFSET |
       1 << DMI_DMCONTROL_AUTHENTICATED_OFFSET),
   abstractcs(datacount << DMI_ABSTRACTCS_DATACOUNT_OFFSET)
@@ -97,7 +98,21 @@ bool debug_module_t::dmi_read(unsigned address, uint32_t *value)
   } else {
     switch (address) {
       case DMI_DMCONTROL:
-        *value = dmcontrol;
+        {
+          processor_t *proc = sim->get_core(get_field(dmcontrol,
+                DMI_DMCONTROL_HARTSEL));
+          if (proc) {
+            D(fprintf(stderr, "(halted=%d) ", proc->halted()));
+            if (proc->halted()) {
+              dmcontrol = set_field(dmcontrol, DMI_DMCONTROL_HARTSTATUS, 0);
+            } else {
+              dmcontrol = set_field(dmcontrol, DMI_DMCONTROL_HARTSTATUS, 1);
+            }
+          } else {
+            dmcontrol = set_field(dmcontrol, DMI_DMCONTROL_HARTSTATUS, 3);
+          }
+          *value = dmcontrol;
+        }
         break;
       case DMI_ABSTRACTCS:
         *value = abstractcs;
diff --git a/riscv/debug_module.h b/riscv/debug_module.h
index d322376..b64a454 100644
--- a/riscv/debug_module.h
+++ b/riscv/debug_module.h
@@ -6,10 +6,12 @@
 
 #include "devices.h"
 
+class sim_t;
+
 class debug_module_t : public abstract_device_t
 {
   public:
-    debug_module_t();
+    debug_module_t(sim_t *sim);
 
     bool load(reg_t addr, size_t len, uint8_t* bytes);
     bool store(reg_t addr, size_t len, const uint8_t* bytes);
@@ -44,6 +46,7 @@ class debug_module_t : public abstract_device_t
     bool dmi_write(unsigned address, uint32_t value);
 
   private:
+    sim_t *sim;
     // Track which interrupts from module to debugger are set.
     std::set<uint32_t> interrupt;
     // Track which halt notifications from debugger to module are set.
diff --git a/riscv/processor.h b/riscv/processor.h
index 8a9ff47..32dc9cd 100644
--- a/riscv/processor.h
+++ b/riscv/processor.h
@@ -192,6 +192,7 @@ public:
   bool debug;
   // When true, take the slow simulation path.
   bool slow_path();
+  bool halted() { return state.dcsr.cause ? true : false; }
 
   // Return the index of a trigger that matched, or -1.
   inline int trigger_match(trigger_operation_t operation, reg_t address, reg_t data)
diff --git a/riscv/sim.cc b/riscv/sim.cc
index 86e23b0..461ae6a 100644
--- a/riscv/sim.cc
+++ b/riscv/sim.cc
@@ -22,7 +22,7 @@ static void handle_signal(int sig)
 
 sim_t::sim_t(const char* isa, size_t nprocs, size_t mem_mb, bool halted,
              const std::vector<std::string>& args)
-  : htif_t(args), procs(std::max(nprocs, size_t(1))),
+  : htif_t(args), debug_module(this), procs(std::max(nprocs, size_t(1))),
     current_step(0), current_proc(0), debug(false), remote_bitbang(NULL)
 {
   signal(SIGINT, &handle_signal);