From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 3 Jun 2020 15:41:55 +0000 (-0700)
Subject: tests: tidy up testcase
X-Git-Tag: working-ls180~512^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8a11019d382f3eb5a8d95ce64511a1dcbbe2acfe;p=yosys.git

tests: tidy up testcase
---

diff --git a/tests/arch/ecp5/latches_abc9.ys b/tests/arch/ecp5/latches_abc9.ys
index ca3182254..4daf04050 100644
--- a/tests/arch/ecp5/latches_abc9.ys
+++ b/tests/arch/ecp5/latches_abc9.ys
@@ -7,9 +7,6 @@ always @*
 assign q = ~l;
 endmodule
 EOT
-proc
-design -save gold
-
 # Can't run any sort of equivalence check because latches are blown to LUTs
 synth_ecp5 -abc9
 select -assert-count 2 t:LUT4