From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 21 May 2018 18:12:25 +0000 (+0100)
Subject: add slide
X-Git-Tag: convert-csv-opcode-to-binary~5346
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8a1123224c4cd7bcde68ac23b4a4b3170916241b;p=libreriscv.git

add slide
---

diff --git a/simple_v_extension/simple_v_chennai_2018.tex b/simple_v_extension/simple_v_chennai_2018.tex
index e760acc14..c9d0df302 100644
--- a/simple_v_extension/simple_v_chennai_2018.tex
+++ b/simple_v_extension/simple_v_chennai_2018.tex
@@ -22,6 +22,20 @@
   \end{center}
 }
 
+
+\frame{\frametitle{The Simon Sinek lowdown (Why, How, What)}
+
+ \begin{itemize}
+   \item Vectorisation needs to fit an implementor's needs:\\
+	     RV32E, Embedded/Mobile, DSP, Servers and more.\vspace{15pt}
+   \item By implicitly marking INT/FP regs as "Vectorised",\\
+	     everything else follows from there.\vspace{15pt}
+   \item A Standard Vector "API" with flexibility for implementors:\\
+	     choice to optimise for area or performance as desired\vspace{10pt}
+  \end{itemize}
+}
+
+
 \frame{\frametitle{Why another Vector Extension?}
 
  \begin{itemize}
@@ -37,6 +51,7 @@
   \end{itemize}
 }
 
+
 \frame{\frametitle{Quick refresher on SIMD}
 
  \begin{itemize}