From: lkcl <lkcl@web>
Date: Fri, 28 Oct 2022 12:26:48 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~36
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8a1145a24644dcff9b2df37136d24d056d46c3d0;p=libreriscv.git

---

diff --git a/openpower/sv/biginteger.mdwn b/openpower/sv/biginteger.mdwn
index 8ff2396d9..02495973d 100644
--- a/openpower/sv/biginteger.mdwn
+++ b/openpower/sv/biginteger.mdwn
@@ -53,22 +53,58 @@ operations.
 
 **DRAFT**
 
-`dsld` and `dsrd` are similar to v3.0 `sld`, and
-is Z23-Form in "overwrite" on RT.
+**dsld**
 
-|0.....5|6..10|11..15|16..20|21.22|23..30|31|
+|0.....5|6..10|11..15|16..20|21.25|26..30|31|
 |-------|-----|------|------|-----|------|--|
-| EXT04 | RT  |  RA  |  RB  | sm  |  XO  |Rc|
-
-Both instructions take two 64-bit sources, concatenate
-them together then extract 64 bits from it, the offset
-location determined by a third source.  So as to avoid
-costly 4-reg (VA-Form) and to allow Vectorised versions
-to use EXTRA3 a 2-bit mode `sm` gives four
-potential overwrite and zero-source options instead
-(a 4-reg VA-Form Vector variant would use EXTRA2,
-limiting the vector offset range and preventing its
-use in biginteger vector-shift operations).
+| EXT04 | RT  |  RA  |  RB  | RC  |  XO  |Rc|
+
+VA2-Form
+
+* dsld    RT,RA,RB,RC  (Rc=0)
+* dsld.   RT,RA,RB,RC  (Rc=1)
+
+Pseudo-code:
+
+    n <- (RB)[58:63]
+    v <- ROTL64((RA), n)
+    mask <- MASK(64, 63-n)
+    RT <- (v[0:63] & mask) | ((RC) & ¬mask)
+    RS <- v[0:63] & ¬mask
+    overflow = 0
+    if RS != [0]*64:
+        overflow = 1
+
+Special Registers Altered:
+
+    CR0                    (if Rc=1)
+
+**dsrd**
+
+|0.....5|6..10|11..15|16..20|21.25|26..30|31|
+|-------|-----|------|------|-----|------|--|
+| EXT04 | RT  |  RA  |  RB  | RC  |  XO  |Rc|
+
+VA2-Form
+
+* dsrd    RT,RA,RB,RC  (Rc=0)
+* dsrd.   RT,RA,RB,RC  (Rc=1)
+
+Pseudo-code:
+
+    n <- (RB)[58:63]
+    v <- ROTL64((RA), 64-n)
+    mask <- MASK(n, 63)
+    RT <- (v[0:63] & mask) | ((RC) & ¬mask)
+    RS <- v[0:63] & ¬mask
+    overflow = 0
+    if RS != [0]*64:
+        overflow = 1
+
+Special Registers Altered:
+
+    CR0                    (if Rc=1)
+
 
 # maddedu