From: Dmitry Selyutin <ghostmansd@gmail.com>
Date: Wed, 17 Aug 2022 18:43:58 +0000 (+0300)
Subject: power_insn: fix sv_extra algorithm
X-Git-Tag: sv_maxu_works-initial~129
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8a144619f8c4d6b86fb9a31c6582de251ed79aa5;p=openpower-isa.git

power_insn: fix sv_extra algorithm
---

diff --git a/src/openpower/decoder/power_insn.py b/src/openpower/decoder/power_insn.py
index cdd7ef98..e0af08d2 100644
--- a/src/openpower/decoder/power_insn.py
+++ b/src/openpower/decoder/power_insn.py
@@ -480,6 +480,9 @@ class Instruction:
         sel = getattr(self.svp64, key)
         if sel is _CRInSel.BA_BB:
             return _SVExtra.Idx_1_2
+        reg = _SVExtraReg(sel)
+        if reg is _SVExtraReg.NONE:
+            return _SVExtra.NONE
 
         extra_map = {
             _SVExtraRegType.SRC: {},
@@ -490,7 +493,7 @@ class Instruction:
                 extra_map[entry.regtype][entry.reg] = Instruction.__EXTRA[index]
 
         for regtype in (_SVExtraRegType.SRC, _SVExtraRegType.DST):
-            extra = extra_map[regtype][sel]
+            extra = extra_map[regtype].get(reg, _SVExtra.NONE)
             if extra is not _SVExtra.NONE:
                 return extra