From: Richard Sandiford <richard.sandiford@arm.com>
Date: Tue, 17 Nov 2020 11:12:52 +0000 (+0000)
Subject: testsuite: Adjust vect/pr65947-8.c for SVE
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8a1f6529062857523988202bad813304f003e8e1;p=gcc.git

testsuite: Adjust vect/pr65947-8.c for SVE

We can vectorise vect/pr65947-8.c for SVE, as we can for GCN.

gcc/testsuite/
	* gcc.dg/vect/pr65947-8.c: Expect the loop to be vectorized for SVE.
---

diff --git a/gcc/testsuite/gcc.dg/vect/pr65947-8.c b/gcc/testsuite/gcc.dg/vect/pr65947-8.c
index a2a940daf1a..d0426792e35 100644
--- a/gcc/testsuite/gcc.dg/vect/pr65947-8.c
+++ b/gcc/testsuite/gcc.dg/vect/pr65947-8.c
@@ -41,6 +41,6 @@ main (void)
   return 0;
 }
 
-/* { dg-final { scan-tree-dump-not "LOOP VECTORIZED" "vect" { target { ! amdgcn*-*-* } } } } */
-/* { dg-final { scan-tree-dump "LOOP VECTORIZED" "vect" { target amdgcn*-*-* } } } */
-/* { dg-final { scan-tree-dump "multiple types in double reduction or condition reduction" "vect" { target { ! amdgcn*-*-* } } } } */
+/* { dg-final { scan-tree-dump-not "LOOP VECTORIZED" "vect" { target { ! { amdgcn*-*-* || aarch64_sve } } } } } */
+/* { dg-final { scan-tree-dump "LOOP VECTORIZED" "vect" { target { amdgcn*-*-* || aarch64_sve } } } } */
+/* { dg-final { scan-tree-dump "multiple types in double reduction or condition reduction" "vect" { target { ! { amdgcn*-*-* || aarch64_sve } } } } } */