From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Fri, 20 Jul 2018 08:01:33 +0000 (+0200)
Subject: build/generic_platform: use list for sources instead of set
X-Git-Tag: 24jan2021_ls180~1664
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8a311bf4a60327bcad31f1ba9c2257556ff94f85;p=litex.git

build/generic_platform: use list for sources instead of set

Ideally, we want to use an ordered set (to be able to keep compilation order), to avoid using an external package, we use a list.
---

diff --git a/litex/build/altera/quartus.py b/litex/build/altera/quartus.py
index 4dae8edf..0dcdb53a 100644
--- a/litex/build/altera/quartus.py
+++ b/litex/build/altera/quartus.py
@@ -127,7 +127,7 @@ class AlteraQuartusToolchain:
         named_sc, named_pc = platform.resolve_signals(v_output.ns)
         v_file = build_name + ".v"
         v_output.write(v_file)
-        sources = platform.sources | {(v_file, "verilog", "work")}
+        sources = platform.sources + [(v_file, "verilog", "work")]
         _build_files(platform.device,
                      sources,
                      platform.verilog_include_paths,
diff --git a/litex/build/generic_platform.py b/litex/build/generic_platform.py
index c4c1e3ba..dbf277de 100644
--- a/litex/build/generic_platform.py
+++ b/litex/build/generic_platform.py
@@ -261,7 +261,7 @@ class GenericPlatform:
         if name is None:
             name = self.__module__.split(".")[-1]
         self.name = name
-        self.sources = set()
+        self.sources = []
         self.verilog_include_paths = set()
         self.finalized = False
 
@@ -323,7 +323,7 @@ class GenericPlatform:
         if library is None:
             library = "work"
 
-        self.sources.add((os.path.abspath(filename), language, library))
+        self.sources.append((os.path.abspath(filename), language, library))
 
     def add_sources(self, path, *filenames, language=None, library=None):
         for f in filenames:
diff --git a/litex/build/lattice/diamond.py b/litex/build/lattice/diamond.py
index e8486e33..276cc408 100644
--- a/litex/build/lattice/diamond.py
+++ b/litex/build/lattice/diamond.py
@@ -110,7 +110,7 @@ class LatticeDiamondToolchain:
         named_sc, named_pc = platform.resolve_signals(v_output.ns)
         v_file = build_name + ".v"
         v_output.write(v_file)
-        sources = platform.sources | {(v_file, "verilog", "work")}
+        sources = platform.sources + [(v_file, "verilog", "work")]
         _build_files(platform.device, sources, platform.verilog_include_paths, build_name)
 
         tools.write_to_file(build_name + ".lpf", _build_lpf(named_sc, named_pc))
diff --git a/litex/build/lattice/icestorm.py b/litex/build/lattice/icestorm.py
index c6463474..7c06f740 100644
--- a/litex/build/lattice/icestorm.py
+++ b/litex/build/lattice/icestorm.py
@@ -173,7 +173,7 @@ class LatticeIceStormToolchain:
         return series_size_str[2:]
 
     def gen_read_files(self, platform, main):
-        sources = platform.sources | {(main, "verilog", "work")}
+        sources = platform.sources + [(main, "verilog", "work")]
         incflags = ""
         read_files = list()
         for path in platform.verilog_include_paths:
diff --git a/litex/build/xilinx/ise.py b/litex/build/xilinx/ise.py
index 5722f530..ef561f4b 100644
--- a/litex/build/xilinx/ise.py
+++ b/litex/build/xilinx/ise.py
@@ -181,7 +181,7 @@ class XilinxISEToolchain:
                 named_sc, named_pc = platform.resolve_signals(vns)
                 v_file = build_name + ".v"
                 v_output.write(v_file)
-                sources = platform.sources | {(v_file, "verilog", "work")}
+                sources = platform.sources + [(v_file, "verilog", "work")]
                 if mode in ("xst", "cpld"):
                     _build_xst_files(platform.device, sources, platform.verilog_include_paths, build_name, self.xst_opt)
                     isemode = mode
diff --git a/litex/build/xilinx/vivado.py b/litex/build/xilinx/vivado.py
index 7a19b75b..3d40e9be 100644
--- a/litex/build/xilinx/vivado.py
+++ b/litex/build/xilinx/vivado.py
@@ -223,7 +223,7 @@ class XilinxVivadoToolchain:
         named_sc, named_pc = platform.resolve_signals(v_output.ns)
         v_file = build_name + ".v"
         v_output.write(v_file)
-        sources = platform.sources | {(v_file, "verilog", "work")}
+        sources = platform.sources + [(v_file, "verilog", "work")]
         edifs = platform.edifs
         ips = platform.ips
         self._build_batch(platform, sources, edifs, ips, build_name)