From: whitequark Date: Mon, 12 Aug 2019 13:37:18 +0000 (+0000) Subject: hdl.xfrm: CEInserter→EnableInserter. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8a3c81dea75025bc7b5dddd40f9ff38c87ecfb78;p=nmigen.git hdl.xfrm: CEInserter→EnableInserter. Fixes #166. --- diff --git a/doc/COMPAT_SUMMARY.md b/doc/COMPAT_SUMMARY.md index 8b1ed53..d81f78a 100644 --- a/doc/COMPAT_SUMMARY.md +++ b/doc/COMPAT_SUMMARY.md @@ -38,8 +38,8 @@ Compatibility summary
Note: `transform_*` methods not considered part of public API. - (⊙) `ModuleTransformer` **brk** - (⊙) `ControlInserter` **brk** - - (-) `CEInserter` **obs** - - (-) `ResetInserter` **obs** + - (+) `CEInserter` → `EnableInserter` + - (+) `ResetInserter` id - (+) `ClockDomainsRenamer` → `DomainRenamer`, `cd_remapping=`→`domain_map=` - (⊙) `edif` **brk** - (+) `module` **obs** → `.hdl.dsl` diff --git a/examples/basic/ctr_ce.py b/examples/basic/ctr_ce.py deleted file mode 100644 index bd20305..0000000 --- a/examples/basic/ctr_ce.py +++ /dev/null @@ -1,35 +0,0 @@ -from nmigen import * -from nmigen.back import rtlil, verilog, pysim - - -class Counter(Elaboratable): - def __init__(self, width): - self.v = Signal(width, reset=2**width-1) - self.o = Signal() - self.ce = Signal() - - def elaborate(self, platform): - m = Module() - m.d.sync += self.v.eq(self.v + 1) - m.d.comb += self.o.eq(self.v[-1]) - return CEInserter(self.ce)(m) - - -ctr = Counter(width=16) - -print(verilog.convert(ctr, ports=[ctr.o, ctr.ce])) - -with pysim.Simulator(ctr, - vcd_file=open("ctrl.vcd", "w"), - gtkw_file=open("ctrl.gtkw", "w"), - traces=[ctr.ce, ctr.v, ctr.o]) as sim: - sim.add_clock(1e-6) - def ce_proc(): - yield; yield; yield - yield ctr.ce.eq(1) - yield; yield; yield - yield ctr.ce.eq(0) - yield; yield; yield - yield ctr.ce.eq(1) - sim.add_sync_process(ce_proc()) - sim.run_until(100e-6, run_passive=True) diff --git a/examples/basic/ctr_en.py b/examples/basic/ctr_en.py new file mode 100644 index 0000000..1b1aec5 --- /dev/null +++ b/examples/basic/ctr_en.py @@ -0,0 +1,35 @@ +from nmigen import * +from nmigen.back import rtlil, verilog, pysim + + +class Counter(Elaboratable): + def __init__(self, width): + self.v = Signal(width, reset=2**width-1) + self.o = Signal() + self.en = Signal() + + def elaborate(self, platform): + m = Module() + m.d.sync += self.v.eq(self.v + 1) + m.d.comb += self.o.eq(self.v[-1]) + return EnableInserter(self.en)(m) + + +ctr = Counter(width=16) + +print(verilog.convert(ctr, ports=[ctr.o, ctr.en])) + +with pysim.Simulator(ctr, + vcd_file=open("ctrl.vcd", "w"), + gtkw_file=open("ctrl.gtkw", "w"), + traces=[ctr.en, ctr.v, ctr.o]) as sim: + sim.add_clock(1e-6) + def ce_proc(): + yield; yield; yield + yield ctr.en.eq(1) + yield; yield; yield + yield ctr.en.eq(0) + yield; yield; yield + yield ctr.en.eq(1) + sim.add_sync_process(ce_proc()) + sim.run_until(100e-6, run_passive=True) diff --git a/nmigen/hdl/__init__.py b/nmigen/hdl/__init__.py index 388d1ce..6f6d6a9 100644 --- a/nmigen/hdl/__init__.py +++ b/nmigen/hdl/__init__.py @@ -4,4 +4,5 @@ from .cd import ClockDomain from .ir import Elaboratable, Fragment, Instance from .mem import Memory from .rec import Record -from .xfrm import DomainRenamer, ResetInserter, CEInserter +from .xfrm import DomainRenamer, ResetInserter, EnableInserter, \ + CEInserter # deprecated diff --git a/nmigen/hdl/xfrm.py b/nmigen/hdl/xfrm.py index 8d853a6..5da98f1 100644 --- a/nmigen/hdl/xfrm.py +++ b/nmigen/hdl/xfrm.py @@ -2,7 +2,7 @@ from abc import ABCMeta, abstractmethod from collections import OrderedDict from collections.abc import Iterable -from ..tools import flatten +from ..tools import flatten, deprecated from .. import tracer from .ast import * from .ast import _StatementList @@ -18,7 +18,7 @@ __all__ = ["ValueVisitor", "ValueTransformer", "DomainCollector", "DomainRenamer", "DomainLowerer", "SampleDomainInjector", "SampleLowerer", "SwitchCleaner", "LHSGroupAnalyzer", "LHSGroupFilter", - "ResetInserter", "CEInserter"] + "ResetInserter", "EnableInserter", "CEInserter"] class ValueVisitor(metaclass=ABCMeta): @@ -657,7 +657,7 @@ class ResetInserter(_ControlInserter): fragment.add_statements(Switch(self.controls[domain], {1: stmts}, src_loc=self.src_loc)) -class CEInserter(_ControlInserter): +class EnableInserter(_ControlInserter): def _insert_control(self, fragment, domain, signals): stmts = [s.eq(s) for s in signals] fragment.add_statements(Switch(self.controls[domain], {0: stmts}, src_loc=self.src_loc)) @@ -671,3 +671,6 @@ class CEInserter(_ControlInserter): en_port = Mux(self.controls[clk_port.domain], en_port, Const(0, len(en_port))) new_fragment.named_ports["EN"] = en_port, en_dir return new_fragment + + +CEInserter = deprecated("instead of `CEInserter`, use `EnableInserter`")(EnableInserter) diff --git a/nmigen/test/test_examples.py b/nmigen/test/test_examples.py index 735731a..bf729c5 100644 --- a/nmigen/test/test_examples.py +++ b/nmigen/test/test_examples.py @@ -18,7 +18,7 @@ class ExamplesTestCase(FHDLTestCase): test_arst = example_test("basic/arst.py") test_cdc = example_test("basic/cdc.py") test_ctr = example_test("basic/ctr.py") - test_ctr_ce = example_test("basic/ctr_ce.py") + test_ctr_en = example_test("basic/ctr_en.py") test_fsm = example_test("basic/fsm.py") test_gpio = example_test("basic/gpio.py") test_inst = example_test("basic/inst.py") diff --git a/nmigen/test/test_hdl_xfrm.py b/nmigen/test/test_hdl_xfrm.py index 24e4f54..4081dd4 100644 --- a/nmigen/test/test_hdl_xfrm.py +++ b/nmigen/test/test_hdl_xfrm.py @@ -437,21 +437,21 @@ class ResetInserterTestCase(FHDLTestCase): """) -class CEInserterTestCase(FHDLTestCase): +class EnableInserterTestCase(FHDLTestCase): def setUp(self): self.s1 = Signal() self.s2 = Signal() self.s3 = Signal() self.c1 = Signal() - def test_ce_default(self): + def test_enable_default(self): f = Fragment() f.add_statements( self.s1.eq(1) ) f.add_driver(self.s1, "sync") - f = CEInserter(self.c1)(f) + f = EnableInserter(self.c1)(f) self.assertRepr(f.statements, """ ( (eq (sig s1) (const 1'd1)) @@ -461,7 +461,7 @@ class CEInserterTestCase(FHDLTestCase): ) """) - def test_ce_cd(self): + def test_enable_cd(self): f = Fragment() f.add_statements( self.s1.eq(1), @@ -470,7 +470,7 @@ class CEInserterTestCase(FHDLTestCase): f.add_driver(self.s1, "sync") f.add_driver(self.s2, "pix") - f = CEInserter({"pix": self.c1})(f) + f = EnableInserter({"pix": self.c1})(f) self.assertRepr(f.statements, """ ( (eq (sig s1) (const 1'd1)) @@ -481,7 +481,7 @@ class CEInserterTestCase(FHDLTestCase): ) """) - def test_ce_subfragment(self): + def test_enable_subfragment(self): f1 = Fragment() f1.add_statements( self.s1.eq(1) @@ -495,7 +495,7 @@ class CEInserterTestCase(FHDLTestCase): f2.add_driver(self.s2, "sync") f1.add_subfragment(f2) - f1 = CEInserter(self.c1)(f1) + f1 = EnableInserter(self.c1)(f1) (f2, _), = f1.subfragments self.assertRepr(f1.statements, """ ( @@ -514,16 +514,16 @@ class CEInserterTestCase(FHDLTestCase): ) """) - def test_ce_read_port(self): + def test_enable_read_port(self): mem = Memory(width=8, depth=4) - f = CEInserter(self.c1)(mem.read_port(transparent=False)).elaborate(platform=None) + f = EnableInserter(self.c1)(mem.read_port(transparent=False)).elaborate(platform=None) self.assertRepr(f.named_ports["EN"][0], """ (m (sig c1) (sig mem_r_en) (const 1'd0)) """) - def test_ce_write_port(self): + def test_enable_write_port(self): mem = Memory(width=8, depth=4) - f = CEInserter(self.c1)(mem.write_port()).elaborate(platform=None) + f = EnableInserter(self.c1)(mem.write_port()).elaborate(platform=None) self.assertRepr(f.named_ports["EN"][0], """ (m (sig c1) (cat (repl (slice (sig mem_w_en) 0:1) 8)) (const 8'd0)) """) @@ -549,13 +549,13 @@ class TransformedElaboratableTestCase(FHDLTestCase): def test_getattr(self): e = _MockElaboratable() - te = CEInserter(self.c1)(e) + te = EnableInserter(self.c1)(e) self.assertIs(te.s1, e.s1) def test_composition(self): e = _MockElaboratable() - te1 = CEInserter(self.c1)(e) + te1 = EnableInserter(self.c1)(e) te2 = ResetInserter(self.c2)(te1) self.assertIsInstance(te1, TransformedElaboratable)