From: Andrew Waterman <andrew@sifive.com>
Date: Fri, 5 May 2017 21:39:26 +0000 (-0700)
Subject: Trap superpage PTEs when PPN LSBs are set
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8a428c769bbde9997551596e324b1f70a66cf6ec;p=riscv-isa-sim.git

Trap superpage PTEs when PPN LSBs are set
---

diff --git a/riscv/mmu.cc b/riscv/mmu.cc
index f0adb22..76a6ab1 100644
--- a/riscv/mmu.cc
+++ b/riscv/mmu.cc
@@ -197,6 +197,8 @@ reg_t mmu_t::walk(reg_t addr, access_type type, reg_t mode)
                type == LOAD ?  !(pte & PTE_R) && !(mxr && (pte & PTE_X)) :
                                !((pte & PTE_R) && (pte & PTE_W))) {
       break;
+    } else if ((ppn & ((reg_t(1) << ptshift) - 1)) != 0) {
+      break;
     } else {
       reg_t ad = PTE_A | ((type == STORE) * PTE_D);
 #ifdef RISCV_ENABLE_DIRTY