From: kajoljain379 <kajoljain797@gmail.com>
Date: Wed, 16 Jan 2019 11:38:45 +0000 (+0530)
Subject: arch-power: Added Radix Tree Page Table Entry
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8a45b656884c71560d82a2070f872cf86bc6456a;p=gem5.git

arch-power: Added Radix Tree Page Table Entry

Change-Id: Ifde9fac352f8019247e8f5f7936c081a3b85d3ac
Signed-off-by: kajoljain379 <kajoljain797@gmail.com>
---

diff --git a/src/arch/power/radixwalk.hh b/src/arch/power/radixwalk.hh
index 3a9efb924..11814e0f1 100644
--- a/src/arch/power/radixwalk.hh
+++ b/src/arch/power/radixwalk.hh
@@ -46,6 +46,21 @@ namespace PowerISA
                 Bitfield<4, 0> NLS;
         EndBitUnion(Rpde)
 
+        BitUnion64(Rpte)
+                Bitfield<63> valid;
+                Bitfield<62> leaf;
+                Bitfield<61> sw1;
+                Bitfield<56,12> rpn;
+                Bitfield<11,9> sw2;
+                Bitfield<8> ref;
+                Bitfield<7> c;
+                Bitfield<5,4> att;
+                Bitfield<3> pri;
+                Bitfield<2> read;
+                Bitfield<1> r_w;
+                Bitfield<0> exe;
+        EndBitUnion(Rpte)
+
         Fault start(ThreadContext * _tc, RequestPtr req, BaseTLB::Mode mode);
         BaseMasterPort &getMasterPort(const std::string &if_name,
                                       PortID idx = InvalidPortID);