From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 24 Jan 2022 13:37:19 +0000 (+0000)
Subject: add cnect2022 presentation
X-Git-Tag: opf_rfc_ls005_v1~3245^2~2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8a4a0d127a0b2fb700de6655219fa02d5e351b6a;p=libreriscv.git

add cnect2022 presentation
---

diff --git a/conferences/ngipointer2021/cnect2022.tex b/conferences/ngipointer2021/cnect2022.tex
new file mode 100644
index 000000000..09abe717e
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+\documentclass[slidestop]{beamer}
+\usepackage{beamerthemesplit}
+\usepackage{graphics}
+\usepackage{pstricks}
+
+\graphicspath{{./}}
+
+\title{The Libre-SOC Gigabit Router ASIC}
+\author{Luke Kenneth Casson Leighton}
+
+
+\begin{document}
+
+\frame{
+   \begin{center}
+    \huge{The Libre-SOC Gigabit Router ASIC}\\
+    \vspace{32pt}
+    \Large{An entirely Libre-Licensed ASIC}\\
+    \Large{with Gigabit Ethernet ports and USB2}\\
+    \Large{and full Libre Firmware}\\
+    \vspace{24pt}
+    \Large{CNECT 2022}\\
+    \vspace{16pt}
+    \large{Sponsored by NGI POINTER and NLnet}\\
+    \vspace{6pt}
+    \large{\today}
+  \end{center}
+}
+
+
+\frame{\frametitle{Why a Libre Gigabit Router?}
+
+ \begin{itemize}
+   \item Most Router ASICs are proprietary\vspace{6pt}
+   \item Persistent GPL violations \vspace{6pt}
+   \item Could contain unknown spying back-doors\\
+         nobody can tell\vspace{6pt}
+   \item Full HDL and Firmware means it's fully-auditable \vspace{6pt}
+  \end{itemize}
+}
+
+
+\frame{\frametitle{Who?}
+
+\vspace{15pt}
+
+ \begin{itemize}
+   \item Luke Leighton (Libre-SOC)\\
+   		 Lead developer \vspace{10pt}
+   \item Jean-Paul Chaput, \\
+   		Dmitry Galayko, \\
+   		Marie-Minerve Louerat\\
+   		 LIP6.fr, Sorbonne University\\
+   		 Developers of Coriolis2 VLSI \vspace{10pt}
+   \item Staf Verhaegen\\
+   		 Chips4Makers.io Belgium\\
+   		 Developer of FlexLib Cell Libraries \vspace{10pt}
+  \end{itemize}
+}
+
+\frame{\frametitle{What?}
+
+\vspace{5pt}
+
+ \begin{itemize}
+   \item Vector Processor based on the Power ISA, (Draft) SVP64
+         Cray Vectors and efficient packet processing instructions
+   \item Gigabit Ethernet Ports (RGMII) USB2 ports (USB-ULPI),
+         GPIO, I2C, QSPI etc.
+   \item DMA Engine to handle fast transfer between Ethernet Ports
+   \item Analog PLL (Libre-Licensed, no NDA)
+   \item Lots of simulations and FPGA testing
+   \item Put it all together: MPW Shuttle Runs\\
+         to be tested, report published
+   \item All entirely Libre-Licensed\\
+         as best we can comply with Foundry NDAs
+  \end{itemize}
+}
+
+\frame{\frametitle{How?}
+
+\vspace{5pt}
+
+ \begin{itemize}
+   \item Entirely in nmigen HDL (python-based, Libre-Licensed)
+   \item Huge ancillary spin-off libraries created:
+   \item IEEE754 pipelined FPU, SIMD Library, I/O HDL Library
+   \item Power ISA now in Machine-readable form
+   \item Coriolis2 VLSI now silicon-proven in 10x larger automated
+   		 layouts (800,000 gates)
+   \item No NDAs, no commercial confidential agreements signed
+         means full Academic and Ethical Freedom to talk about
+         what we did and how we did it
+  \end{itemize}
+}
+
+
+\frame{
+  \begin{center}
+    {\Large The end\vspace{12pt}\\
+		   Thank you\vspace{12pt}\\
+		   Questions?\vspace{12pt}
+	}
+  \end{center}
+
+  \begin{itemize}
+	\item Discussion: http://lists.libre-soc.org
+	\item Libera IRC \#libre-soc
+	\item http://libre-soc.org/
+	\item http://coriolis.lip6.fr
+	\item http://chips4makers.io
+  \end{itemize}
+}
+
+
+\end{document}