From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 25 Sep 2021 17:59:15 +0000 (+0100)
Subject: move coresync clock synchronisation into HDLRunner
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8a51f6944fa6c5185285b0139f5b419fb68aa145;p=soc.git

move coresync clock synchronisation into HDLRunner
---

diff --git a/src/soc/simple/test/test_runner.py b/src/soc/simple/test/test_runner.py
index 223d9478..130462e0 100644
--- a/src/soc/simple/test/test_runner.py
+++ b/src/soc/simple/test/test_runner.py
@@ -198,6 +198,10 @@ class HDLRunner(StateRunner):
         comb += self.issuer.pc_i.data.eq(self.pc_i)
         comb += self.issuer.svstate_i.data.eq(self.svstate_i)
 
+        # run core clock at same rate as test clock
+        intclk = ClockSignal("coresync")
+        comb += intclk.eq(ClockSignal())
+
     def prepare_for_test(self, test):
         self.test = test
 
@@ -377,10 +381,6 @@ class TestRunner(FHDLTestCase):
         if self.run_sim:
             simrun = SimRunner(self, m, pspec)
 
-        # run core clock at same rate as test clock
-        intclk = ClockSignal("coresync")
-        comb += intclk.eq(ClockSignal())
-
         # nmigen Simulation - everything runs around this, so it
         # still has to be created.
         sim = Simulator(m)