From: Clifford Wolf <clifford@clifford.at>
Date: Mon, 7 Jan 2019 09:01:11 +0000 (+0100)
Subject: Bugfix in $memrd sharing
X-Git-Tag: yosys-0.9~335
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8a63fc51d31bca50c3d08130c3271a288af1cf4b;p=yosys.git

Bugfix in $memrd sharing

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---

diff --git a/passes/opt/share.cc b/passes/opt/share.cc
index b80280829..c85c27427 100644
--- a/passes/opt/share.cc
+++ b/passes/opt/share.cc
@@ -710,8 +710,12 @@ struct ShareWorker
 			RTLIL::Cell *supercell = module->addCell(NEW_ID, c1);
 			RTLIL::SigSpec addr1 = c1->getPort("\\ADDR");
 			RTLIL::SigSpec addr2 = c2->getPort("\\ADDR");
-			if (addr1 != addr2)
-				supercell->setPort("\\ADDR", module->Mux(NEW_ID, addr2, addr1, act));
+			if (GetSize(addr1) < GetSize(addr2))
+				addr1.extend_u0(GetSize(addr2));
+			else
+				addr2.extend_u0(GetSize(addr1));
+			supercell->setPort("\\ADDR", addr1 != addr2 ? module->Mux(NEW_ID, addr2, addr1, act) : addr1);
+			supercell->parameters["\\ABITS"] = RTLIL::Const(GetSize(addr1));
 			supercell_aux.insert(module->addPos(NEW_ID, supercell->getPort("\\DATA"), c2->getPort("\\DATA")));
 			supercell_aux.insert(supercell);
 			return supercell;