From: Eric Botcazou <ebotcazou@libertysurf.fr>
Date: Sat, 31 May 2003 07:53:13 +0000 (+0200)
Subject: md.texi (Machine Constraints): Document missing SPARC constraints.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8a69f99fc9ba625676c93c510e1302fae80874f6;p=gcc.git

md.texi (Machine Constraints): Document missing SPARC constraints.

	* doc/md.texi (Machine Constraints): Document
	missing SPARC constraints.

From-SVN: r67263
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 18bc820c4b2..05ba8ae6d33 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2003-05-31  Eric Botcazou  <ebotcazou@libertysurf.fr>
+
+	* doc/md.texi (Machine Constraints): Document
+	missing SPARC constraints.
+
 2003-05-31  Eric Botcazou  <ebotcazou@libertysurf.fr>
 
 	* doc/md.texi (Automaton pipeline description): Use
diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index 0ef948ad171..665e34940ee 100644
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -2020,6 +2020,22 @@ Floating-point register that can hold 32- or 64-bit values.
 @item e
 Floating-point register that can hold 64- or 128-bit values.
 
+@item c
+Floating-point condition code register.
+
+@item d
+Floating-point register that can hold 32- or 64-bit values.
+It is only valid on the SPARC-V9 architecture when the Visual
+Instructions Set is available.
+
+@item b
+Floating-point register that can hold 64- or 128-bit values.
+It is only valid on the SPARC-V9 architecture when the Visual
+Instructions Set is available.
+
+@item h
+64-bit global or out register for the SPARC-V8+ architecture.
+
 @item I
 Signed 13-bit constant