From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 11 Jun 2019 19:02:31 +0000 (-0700)
Subject: Remove #ifndef ABC
X-Git-Tag: working-ls180~1208^2~167
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8a708d1fdb662f86a46720200fa15acafde30333;p=yosys.git

Remove #ifndef ABC
---

diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index 88967b068..14e35737e 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -295,10 +295,8 @@ module RAM64X1D (
   reg [63:0] mem = INIT;
   assign SPO = mem[a];
   assign DPO = mem[dpra];
-`ifndef _ABC
   wire clk = WCLK ^ IS_WCLK_INVERTED;
   always @(posedge clk) if (WE) mem[a] <= D;
-`endif
 endmodule
 
 (* abc_box_id = 5 /*, lib_whitebox*/ *)
@@ -312,10 +310,8 @@ module RAM128X1D (
   reg [127:0] mem = INIT;
   assign SPO = mem[A];
   assign DPO = mem[DPRA];
-`ifndef _ABC
   wire clk = WCLK ^ IS_WCLK_INVERTED;
   always @(posedge clk) if (WE) mem[A] <= D;
-`endif
 endmodule
 
 module SRL16E (