From: Luke Kenneth Casson Leighton Date: Sat, 31 Jul 2021 13:19:46 +0000 (+0100) Subject: add i-DCT SVP64 unit test for outer butterfly X-Git-Tag: xlen-bcd~173 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8a728fe29d7184b083a49152b35b2700c6c95a97;p=openpower-isa.git add i-DCT SVP64 unit test for outer butterfly --- diff --git a/openpower/isa/simplev.mdwn b/openpower/isa/simplev.mdwn index 00410112..2971ace1 100644 --- a/openpower/isa/simplev.mdwn +++ b/openpower/isa/simplev.mdwn @@ -205,11 +205,12 @@ Pseudo-code: # set up FRB and FRS SVSHAPE0[0:5] <- (0b0 || SVxd) # xdim if (SVRM = 0b1011) then - SVSHAPE0[30:31] <- 0b11 # iDCT mode - SVSHAPE0[18:20] <- 0b011 # iDCT Outer Butterfly sub-mode + SVSHAPE0[30:31] <- 0b11 # iDCT mode + SVSHAPE0[18:20] <- 0b011 # iDCT Outer Butterfly sub-mode + SVSHAPE0[21:23] <- 0b101 # "inverse" on outer and inner loop else - SVSHAPE0[30:31] <- 0b01 # DCT mode - SVSHAPE0[18:20] <- 0b100 # DCT Outer Butterfly sub-mode + SVSHAPE0[30:31] <- 0b01 # DCT mode + SVSHAPE0[18:20] <- 0b100 # DCT Outer Butterfly sub-mode SVSHAPE0[6:11] <- 0b000010 # DCT Butterfly mode # copy SVSHAPE1[0:31] <- SVSHAPE0[0:31] diff --git a/src/openpower/decoder/isa/svshape.py b/src/openpower/decoder/isa/svshape.py index 88484ba2..f9de391b 100644 --- a/src/openpower/decoder/isa/svshape.py +++ b/src/openpower/decoder/isa/svshape.py @@ -118,7 +118,7 @@ class SVSHAPE(SelectableInt): log ("SVSHAPE get_iterator", self.mode, self.ydimsz) if self.mode == 0b00: iterate_fn = iterate_indices - elif self.mode == 0b01: + elif self.mode in [0b01, 0b11]: # further sub-selection if self.ydimsz == 1: iterate_fn = iterate_butterfly_indices diff --git a/src/openpower/decoder/isa/test_caller_svp64_dct.py b/src/openpower/decoder/isa/test_caller_svp64_dct.py index dae3369e..53537ffb 100644 --- a/src/openpower/decoder/isa/test_caller_svp64_dct.py +++ b/src/openpower/decoder/isa/test_caller_svp64_dct.py @@ -18,7 +18,7 @@ import unittest import math -def transform_inner_radix2(vec, ctable): +def transform_inner_radix2_dct(vec, ctable): # Initialization n = len(vec) @@ -80,7 +80,8 @@ def transform_inner_radix2(vec, ctable): return vec -def transform_outer_radix2(vec): + +def transform_outer_radix2_dct(vec): # Initialization n = len(vec) @@ -127,6 +128,119 @@ def transform_outer_radix2(vec): return vec +def transform_inner_radix2_idct(vec, ctable): + + # Initialization + n = len(vec) + print () + print ("transform2", n) + levels = n.bit_length() - 1 + + # pretend we LDed data in half-swapped order + vec = halfrev2(vec, True) + + ################ + # INNER butterfly + ################ + xdim = n + ydim = 0 + zdim = 0 + + # set up an SVSHAPE + class SVSHAPE: + pass + # j schedule + SVSHAPE0 = SVSHAPE() + SVSHAPE0.lims = [xdim, 0b000001, 0] + SVSHAPE0.mode = 0b11 + SVSHAPE0.submode2 = 0b11 + SVSHAPE0.skip = 0b00 + SVSHAPE0.offset = 0 # experiment with different offset, here + SVSHAPE0.invxyz = [0,0,0] # inversion if desired + # j+halfstep schedule + SVSHAPE1 = SVSHAPE() + SVSHAPE1.lims = [xdim, 0b000001, 0] + SVSHAPE1.mode = 0b11 + SVSHAPE1.submode2 = 0b11 + SVSHAPE1.skip = 0b01 + SVSHAPE1.offset = 0 # experiment with different offset, here + SVSHAPE1.invxyz = [0,0,0] # inversion if desired + + # enumerate over the iterator function, getting new indices + i0 = iterate_dct_inner_butterfly_indices(SVSHAPE0) + i1 = iterate_dct_inner_butterfly_indices(SVSHAPE1) + for k, ((jl, jle), (jh, jhe)) in enumerate(zip(i0, i1)): + t1, t2 = vec[jl], vec[jh] + coeff = ctable[k] + vec[jl] = t1 + t2 + vec[jh] = (t1 - t2) * (1.0/coeff) + print ("coeff", "ci", k, + "jl", jl, "jh", jh, + "i/n", (k+0.5), 1.0/coeff, + "t1, t2", t1, t2, "res", vec[jl], vec[jh], + "end", bin(jle), bin(jhe)) + if jle == 0b111: # all loops end + break + + return vec + + +def transform_outer_radix2_idct(vec): + + # Initialization + n = len(vec) + print () + print ("transform2-inv", n) + levels = n.bit_length() - 1 + + # outer butterfly + xdim = n + ydim = 0 + zdim = 0 + + # reference (read/write) the in-place data in *reverse-bit-order* + ri = list(range(n)) + ri = [ri[reverse_bits(i, levels)] for i in range(n)] + + # and pretend we LDed data in half-swapped *and* bit-reversed order as well + # TODO: merge these two + vec = [vec[ri[i]] for i in range(n)] + vec = halfrev2(vec, True) + + # j schedule + class SVSHAPE: + pass + SVSHAPE0 = SVSHAPE() + SVSHAPE0.lims = [xdim, 3, zdim] + SVSHAPE0.submode2 = 0b011 + SVSHAPE0.mode = 0b11 + SVSHAPE0.skip = 0b00 + SVSHAPE0.offset = 0 # experiment with different offset, here + SVSHAPE0.invxyz = [1,0,1] # inversion if desired + # j+halfstep schedule + SVSHAPE1 = SVSHAPE() + SVSHAPE1.lims = [xdim, 3, zdim] + SVSHAPE1.mode = 0b11 + SVSHAPE1.submode2 = 0b011 + SVSHAPE1.skip = 0b01 + SVSHAPE1.offset = 0 # experiment with different offset, here + SVSHAPE1.invxyz = [1,0,1] # inversion if desired + + # enumerate over the iterator function, getting new indices + i0 = iterate_dct_outer_butterfly_indices(SVSHAPE0) + i1 = iterate_dct_outer_butterfly_indices(SVSHAPE1) + for k, ((jl, jle), (jh, jhe)) in enumerate(zip(i0, i1)): + print ("itersum jr", jl, jh, + "end", bin(jle), bin(jhe)) + vec[jl] += vec[jh] + if jle == 0b111: # all loops end + break + + print("transform2-inv result", vec) + + return vec + + class DCTTestCase(FHDLTestCase): def _check_regs(self, sim, expected): @@ -245,7 +359,65 @@ class DCTTestCase(FHDLTestCase): print ("spr svshape3", sim.spr['SVSHAPE3']) # work out the results with the twin mul/add-sub - res = transform_inner_radix2(avi, coe) + res = transform_inner_radix2_dct(avi, coe) + + for i, expected in enumerate(res): + print ("i", i, float(sim.fpr(i)), "expected", expected) + for i, expected in enumerate(res): + # convert to Power single + expected = DOUBLE2SINGLE(fp64toselectable(expected)) + expected = float(expected) + actual = float(sim.fpr(i)) + # approximate error calculation, good enough test + # reason: we are comparing FMAC against FMUL-plus-FADD-or-FSUB + # and the rounding is different + err = abs((actual - expected) / expected) + print ("err", i, err) + self.assertTrue(err < 1e-6) + + def test_sv_remap_fpmadds_idct_outer_8(self): + """>>> lst = ["svshape 8, 1, 1, 11, 0", + "svremap 27, 1, 0, 2, 0, 1, 0", + "sv.fadds 0.v, 0.v, 0.v" + ] + runs a full in-place 8-long O(N log2 N) outer butterfly schedule + for inverse-DCT, does the iterative overlapped ADDs + + SVP64 "REMAP" in Butterfly Mode. + """ + lst = SVP64Asm( ["svshape 8, 1, 1, 11, 0", + "svremap 27, 1, 0, 2, 0, 1, 0", + "sv.fadds 0.v, 0.v, 0.v" + ]) + lst = list(lst) + + # array and coefficients to test + avi = [7.0, -9.8, 3.0, -32.3, 2.1, 3.6, 0.7, -0.2] + + n = len(avi) + levels = n.bit_length() - 1 + ri = list(range(n)) + ri = [ri[reverse_bits(i, levels)] for i in range(n)] + av = [avi[ri[i]] for i in range(n)] + av = halfrev2(av, True) + + # store in regfile + fprs = [0] * 32 + for i, a in enumerate(av): + fprs[i+0] = fp64toselectable(a) + + with Program(lst, bigendian=False) as program: + sim = self.run_tst_program(program, initial_fprs=fprs) + print ("spr svshape0", sim.spr['SVSHAPE0']) + print (" xdimsz", sim.spr['SVSHAPE0'].xdimsz) + print (" ydimsz", sim.spr['SVSHAPE0'].ydimsz) + print (" zdimsz", sim.spr['SVSHAPE0'].zdimsz) + print ("spr svshape1", sim.spr['SVSHAPE1']) + print ("spr svshape2", sim.spr['SVSHAPE2']) + print ("spr svshape3", sim.spr['SVSHAPE3']) + + # outer iterative sum + res = transform_outer_radix2_idct(avi) for i, expected in enumerate(res): print ("i", i, float(sim.fpr(i)), "expected", expected) @@ -296,7 +468,7 @@ class DCTTestCase(FHDLTestCase): print ("spr svshape3", sim.spr['SVSHAPE3']) # outer iterative sum - res = transform_outer_radix2(av) + res = transform_outer_radix2_dct(av) for i, expected in enumerate(res): print ("i", i, float(sim.fpr(i)), "expected", expected)