From: Xan Date: Wed, 25 Apr 2018 05:46:50 +0000 (+0100) Subject: (no commit message) X-Git-Tag: convert-csv-opcode-to-binary~5547 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8a8c058f978a8864627172be40b2a1bfa09a4587;p=libreriscv.git --- diff --git a/A_Harmonised_RVV_and_Packed_SIMD.mdwn b/A_Harmonised_RVV_and_Packed_SIMD.mdwn index 452c4cf1c..bb583c75e 100644 --- a/A_Harmonised_RVV_and_Packed_SIMD.mdwn +++ b/A_Harmonised_RVV_and_Packed_SIMD.mdwn @@ -111,3 +111,23 @@ The “K” (Saturation) and “u” (Rounding) variants could be encoded using | KSLRA16 rt, ra, rb | Saturating Shift left logical or Shift right arithmetic || | KSLRA16.u rt, ra, rb | Saturating Shift left logical or Rounding Shift right arithmetic || + +## 8-bit Shifts + +Andes SIMD Packed ISA omits 8 bit shifts, but these can be encoded in Harmonised RVP as follows: + +| Mnemonic | 8-bit Instruction | Harmonised RVP Equivalent | +| ------------------ | ------------------------- | ------------------- | +| | Shift right arithmetic | VSRA (r2 <= rt,ra,rb <= r15), mm=00| +| | Shift right arithmetic imm | VSRAI (r2 <= rt,ra <= r15), mm=00| +| | Rounding Shift right arithmetic | VSRA (r2 <= rt,ra,rb <= r15), mm=01| +| | Rounding Shift right arithmetic imm | VSRAI (r2 <= rt,ra <= r15), mm=01| +| | Shift right logical | VSRL (r2 <= rt,ra,rb <= r15), mm=00| +| | Shift right logical imm | VSRLI (r2 <= rt,ra <= r15), mm=00| +| | Rounding Shift right logical | VSRL (r2 <= rt,ra,rb <= r15), mm=01| +| | Rounding Shift right logical imm | VSLRI (r2 <= rt,ra <= r15), mm=01| +| | Shift left logical | VSLL (r2 <= rt,ra,rb <= r15), mm=00| +| | Shift left logical imm | VSLLI (r2 <= rt,ra <= r15), mm=00| +| | Saturating Shift left logical | VSLL (r2 <= rt,ra,rb <= r15), mm=01| +| | Saturating Shift left logical imm | VSLLI (r2 <= rt,ra <= r15), mm=01| +