From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 1 May 2021 12:22:30 +0000 (+0100)
Subject: missing self.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8a8e2c01cd4e9ef560b8a9cb29f59ffee5ff0420;p=soc.git

missing self.
---

diff --git a/src/soc/experiment/l0_cache.py b/src/soc/experiment/l0_cache.py
index 43bee1e9..8414f77f 100644
--- a/src/soc/experiment/l0_cache.py
+++ b/src/soc/experiment/l0_cache.py
@@ -326,7 +326,7 @@ class TstL0CacheBuffer(Elaboratable):
 
         # really bad hack, the LoadStore1 classes already have the
         # lsi (LoadStoreInterface) as a submodule.
-        if pspec.ldst_ifacetype in ['mmu_cache_wb', 'test_mmu_cache_wb']:
+        if self.pspec.ldst_ifacetype in ['mmu_cache_wb', 'test_mmu_cache_wb']:
             return m
 
         # hmmm not happy about this - should not be digging down and