From: lkcl <lkcl@web>
Date: Mon, 10 May 2021 17:23:01 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~935
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8a91162a27411d4f932363cf36e7da99aff9f8f6;p=libreriscv.git

---

diff --git a/openpower/sv/implementation.mdwn b/openpower/sv/implementation.mdwn
index 39cb7ff24..b9d8e85a5 100644
--- a/openpower/sv/implementation.mdwn
+++ b/openpower/sv/implementation.mdwn
@@ -141,11 +141,13 @@ Links:
 
 SV's SVSTATE context is effectively a Sub-PC.  On exceptions the PC is saved into SRR0: it should come as no surprise that SVSTATE must be treated exactly the same.  SVSRR0 therefore is added to the list to be saved/restored in **exactly** the same way and time as SRR0 and SRR1.  This is fundamental and absolutely critical to view SVSTATE as a full peer of PC (CIA, NIA).
 
-* ISACaller: TODO
+* ISACaller: TODO unit test
 * power-gem5: TODO
 * TestIssuer: TODO
 * Microwatt: TODO
 
+* added ISACaller SVSRR0 save <https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=25071d491dba94495657796eb6ff10eb6499257f>
+
 ## Illegal instruction exceptions
 
 Anything not listed as SVP64 extended must raise an illegal exception if prefixed. setvl, branch, mtmsr, mfmsr at the minimum.