From: lkcl <lkcl@web>
Date: Fri, 22 Jan 2021 16:27:07 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~384
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8ab8024b418f4cf55cbb455b858bdecddb07b6e5;p=libreriscv.git

---

diff --git a/openpower/sv/implementation.mdwn b/openpower/sv/implementation.mdwn
index 3a7514bc7..8e1e4b59c 100644
--- a/openpower/sv/implementation.mdwn
+++ b/openpower/sv/implementation.mdwn
@@ -29,6 +29,8 @@ incremental feature.
 These are prerequisite tasks:
 
 * power-gem5 automanagement, similar to pygdbmi for starting qemu
+  found this <https://www.gem5.org/documentation/general_docs/debugging_and_testing/debugging/debugging_simulated_code>
+  just use pygdbmi
 * c++, c and python macros for generating [[sv/svp64]] assembler
   (svp64 prefixes)