From: lkcl <lkcl@web>
Date: Thu, 12 May 2022 12:02:34 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2260
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8ac2309714e8b8b7f29d91ce972a5768d102e618;p=libreriscv.git

---

diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn
index 79d0441d4..5aadeb1f1 100644
--- a/openpower/sv/SimpleV_rationale.mdwn
+++ b/openpower/sv/SimpleV_rationale.mdwn
@@ -1020,7 +1020,12 @@ with the proposed microarchitecture: the differences however are key.
   being a bit light on L1 Cache, in favour of large ALUs and proximity
   to Memory, and require a modest amount of "helper" assistance with
   their Virtual Memory Management.
-
+* ZOLC has the transition points where PEs may take over from the CPU
+  actually embedded into the binary, and there is accompanying
+  hardware-level assistance at the ISA level.  GPUs, which have to
+  work with a wide range of commidity CPUs, cannot in any way expect
+  ARM or Intel to add support for GPU Task Scheduling directly into
+  the ARM or x86 ISAs!
 
 **Roadmap summary of Advanced SVP64**