From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Date: Tue, 24 Sep 2019 02:17:42 +0000 (+1000)
Subject: Simplify fetch1
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8af2b004c389aeb65e12621eb59f5416706268f1;p=microwatt.git

Simplify fetch1

Do the +4 in a single place. This shouldn't cause any difference
in behaviour as these are sequential variable assignments.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---

diff --git a/fetch1.vhdl b/fetch1.vhdl
index 29ff71f..643e8c8 100644
--- a/fetch1.vhdl
+++ b/fetch1.vhdl
@@ -49,19 +49,18 @@ begin
 
 	if stall_in = '0' then
 	    v.nia := r_int.nia_next;
-	    v_int.nia_next := std_logic_vector(unsigned(r_int.nia_next) + 4);
 	end if;
 
 	if e_in.redirect = '1' then
 	    v.nia := e_in.redirect_nia;
-	    v_int.nia_next := std_logic_vector(unsigned(e_in.redirect_nia) + 4);
 	end if;
 
 	if rst = '1' then
 	    v.nia := RESET_ADDRESS;
-	    v_int.nia_next := std_logic_vector(unsigned(RESET_ADDRESS) + 4);
 	end if;
 
+	v_int.nia_next := std_logic_vector(unsigned(v.nia) + 4);
+
 	-- Update registers
 	rin <= v;
 	rin_int <= v_int;