From: Dmitry Selyutin <ghostmansd@gmail.com>
Date: Sun, 18 Sep 2022 19:34:25 +0000 (+0300)
Subject: power_insn: introduce common mr/mrr RM class
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8b105b325f39416cb9501cf1598d0564befce86e;p=openpower-isa.git

power_insn: introduce common mr/mrr RM class
---

diff --git a/src/openpower/decoder/power_insn.py b/src/openpower/decoder/power_insn.py
index 933c9009..1ef94d38 100644
--- a/src/openpower/decoder/power_insn.py
+++ b/src/openpower/decoder/power_insn.py
@@ -1361,6 +1361,16 @@ class SZBaseRM(BaseRM):
         yield from super().specifiers(record=record)
 
 
+class MRBaseRM(BaseRM):
+    def specifiers(self, record):
+        if self.RG:
+            yield "mrr"
+        else:
+            yield "mr"
+
+        yield from super().specifiers(record=record)
+
+
 class NormalLDSTBaseRM(BaseRM):
     def specifiers(self, record):
         widths = {
@@ -1433,16 +1443,10 @@ class NormalSimpleRM(DZBaseRM, SZBaseRM, NormalBaseRM):
         yield from super().specifiers(record=record)
 
 
-class NormalSMRRM(NormalBaseRM):
+class NormalSMRRM(MRBaseRM, NormalBaseRM):
     """normal: scalar reduce mode (mapreduce), SUBVL=1"""
     RG: BaseRM.mode[4]
 
-    def specifiers(self, record):
-        if self.RG:
-            yield "mrr"
-
-        yield from super().specifiers(record=record)
-
 
 class NormalReservedRM(NormalBaseRM):
     """normal: reserved"""
@@ -1651,32 +1655,20 @@ class CROpBaseRM(BaseRM):
     SNZ: BaseRM[7]
 
 
-class CROpSimpleRM(DZBaseRM, SZBaseRM, CROpBaseRM):
+class CROpSimpleRM(MRBaseRM, DZBaseRM, SZBaseRM, CROpBaseRM):
     """cr_op: simple mode"""
     RG: BaseRM[20]
     sz: BaseRM[21]
     dz: BaseRM[22]
     sz: BaseRM[23]
 
-    def specifiers(self, record):
-        if self.RG:
-            yield "mrr"
-
-        yield from super().specifiers(record=record)
-
 
-class CROpSMRRM(DZBaseRM, SZBaseRM, CROpBaseRM):
+class CROpSMRRM(MRBaseRM, DZBaseRM, SZBaseRM, CROpBaseRM):
     """cr_op: scalar reduce mode (mapreduce), SUBVL=1"""
     RG: BaseRM[20]
     dz: BaseRM[22]
     sz: BaseRM[23]
 
-    def specifiers(self, record):
-        if self.RG:
-            yield "mrr"
-
-        yield from super().specifiers(record=record)
-
 
 class CROpFF3RM(ZZBaseRM, CROpBaseRM):
     """cr_op: ffirst 3-bit mode"""