From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 30 Sep 2019 22:34:04 +0000 (-0700)
Subject: Add quick test
X-Git-Tag: working-ls180~1020^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8b239ee707a2bf4a868728046d7f64c16d74aa2a;p=yosys.git

Add quick test
---

diff --git a/tests/techmap/aigmap.ys b/tests/techmap/aigmap.ys
new file mode 100644
index 000000000..a40aa39f1
--- /dev/null
+++ b/tests/techmap/aigmap.ys
@@ -0,0 +1,10 @@
+read_verilog <<EOT
+module top(input i, j, s, output o, p);
+assign o = s ? j : i;
+assign p = ~i;
+endmodule
+EOT
+
+select t:$mux
+aigmap -select
+select -assert-any %