From: Jacob Lifshay <programmerjake@gmail.com>
Date: Sun, 3 Dec 2023 08:46:01 +0000 (-0800)
Subject: Mem: speed up log_fancy by using make_sim_state_dict()
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8b2d7e8746e94c0b61e6ba0fdb1e170308b0aef5;p=openpower-isa.git

Mem: speed up log_fancy by using make_sim_state_dict()
---

diff --git a/src/openpower/decoder/isa/mem.py b/src/openpower/decoder/isa/mem.py
index a5867f3d..c4744b87 100644
--- a/src/openpower/decoder/isa/mem.py
+++ b/src/openpower/decoder/isa/mem.py
@@ -268,10 +268,10 @@ class MemCommon:
             return bytearray(line_size)
         mem_lines = defaultdict(make_line)
         subword_range = range(1 << self.word_log2)
-        for k in self.word_idxs():
-            addr = k << self.word_log2
-            for _ in subword_range:
-                v = self.ld(addr, width=1, reason=_ReadReason.Dump)
+        words = self.make_sim_state_dict()
+        for addr, word in words.items():
+            for i in subword_range:
+                v = (word >> i * 8) & 0xFF
                 mem_lines[addr >> log2_line_size][addr & subline_mask] = v
                 addr += 1