From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 1 Aug 2013 18:02:15 +0000 (+0200)
Subject: Updated TODO section in README
X-Git-Tag: yosys-0.2.0~523
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8b2f7792ba7a1f4c42f6185a24bd49c6f6985863;p=yosys.git

Updated TODO section in README
---

diff --git a/README b/README
index 7df3c400e..d8d27b356 100644
--- a/README
+++ b/README
@@ -238,14 +238,6 @@ Verilog Attributes and non-standard features
 TODOs / Open Bugs
 =================
 
-- Write "design and implementation of.." document
-
-  - Source tree layout
-  - Data formats (c++ classes, etc.)
-  - Internal misc. frameworks (log, select)
-  - Build system and pass registration
-  - Internal cell library
-
 - Implement missing Verilog 2005 features:
 
   - Signed constants
@@ -264,7 +256,7 @@ TODOs / Open Bugs
   - Implement mux-to-tribuf pass and rebalance mixed mux/tribuf trees
   - Add edit commands for changing the design (delete, add, modify objects)
   - Improve TCL support (add mechanism for inspecting the design from TCL)
-  - Additional internal cell types: $pla and $lut
+  - Add full support for $lut cell type (const evaluation, sat solving, etc.)
   - Support for registering designs (as collection of modules) to CellTypes
   - Smarter resource sharing pass (add MUXes and get rid of duplicated cells)
   - Refactoring of AST frontend (clean expr width/sign code, AST passes)