From: Michael Nolan Date: Tue, 31 Mar 2020 19:19:02 +0000 (-0400) Subject: Begin adding cordic X-Git-Tag: ls180-24jan2020~109 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8b2fa32605883cd870325278ea4f08a84da94611;p=ieee754fpu.git Begin adding cordic --- diff --git a/src/ieee754/cordic/fptan.py b/src/ieee754/cordic/fptan.py new file mode 100644 index 00000000..d3f54ccd --- /dev/null +++ b/src/ieee754/cordic/fptan.py @@ -0,0 +1,76 @@ +from nmigen import Module, Elaboratable, Signal, Cat, Mux +from nmigen.cli import rtlil +import math +from enum import Enum, unique + +class CordicState(Enum): + WAITING = 0 + RUNNING = 1 + + +class CORDIC(Elaboratable): + def __init__(self, fracbits): + self.fracbits = fracbits + self.M = M = (1<> i) + sync += dx.eq(y >> i) + + return m + def ports(self): + return [self.cos, self.sin, self.z0, + self.ready, self.start] + +if __name__ == '__main__': + dut = CORDIC(8) + vl = rtlil.convert(dut, ports=dut.ports()) + with open("cordic.il", "w") as f: + f.write(vl) +