From: Andrew Waterman <andrew@sifive.com>
Date: Thu, 2 Nov 2017 01:57:02 +0000 (-0700)
Subject: Don't permit delegation of interrupts that M-mode should handle
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8b389440b7aff4cf7f81dd17babc649abec810b3;hp=3b1e9ab7522b3b20cde6bd8d9f2b28222463cf1b;p=riscv-isa-sim.git

Don't permit delegation of interrupts that M-mode should handle
---

diff --git a/riscv/processor.cc b/riscv/processor.cc
index ae02165..203394b 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -360,10 +360,9 @@ void processor_t::set_csr(int which, reg_t val)
       state.mideleg = (state.mideleg & ~delegable_ints) | (val & delegable_ints);
       break;
     case CSR_MEDELEG: {
-      reg_t mask = 0;
-#define DECLARE_CAUSE(name, value) mask |= 1ULL << (value);
-#include "encoding.h"
-#undef DECLARE_CAUSE
+      reg_t mask = CAUSE_MISALIGNED_FETCH | CAUSE_BREAKPOINT
+                 | CAUSE_USER_ECALL | CAUSE_FETCH_PAGE_FAULT
+                 | CAUSE_LOAD_PAGE_FAULT | CAUSE_STORE_PAGE_FAULT;
       state.medeleg = (state.medeleg & ~mask) | (val & mask);
       break;
     }