From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 13 Aug 2019 10:53:12 +0000 (+0100)
Subject: add swizzle description to abridged sv spec
X-Git-Tag: convert-csv-opcode-to-binary~4215
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8b38daf4ee6e066dc16b433b89b3566b32b67c92;p=libreriscv.git

add swizzle description to abridged sv spec
---

diff --git a/simple_v_extension/abridged_spec.mdwn b/simple_v_extension/abridged_spec.mdwn
index f5a607ab5..86c10714c 100644
--- a/simple_v_extension/abridged_spec.mdwn
+++ b/simple_v_extension/abridged_spec.mdwn
@@ -221,6 +221,23 @@ Pseudocode for predication:
 [[!inline raw="yes" pages="simple_v_extension/pred_table" ]]
 [[!inline raw="yes" pages="simple_v_extension/get_pred_value" ]]
 
+## Swizzle Table <a name="swizzle_table></a>
+
+The swizzle table is a key-value store that indicates (if a given
+register is used, and SUBVL is 2, 3 or 4) that the sub-elements are to
+be re-ordered according to the indices in the Swizzle format.
+
+Source vectors are free to have the swizzle indices point to the same
+sub-vector element.  However when using swizzling on destination vectors,
+the swizzle **must** be a permutation (no two swizzle indices point to
+the same sub-element).  An illegal instruction exception must be raised
+if this occurs.
+
+[[!inline raw="yes" pages="simple_v_extension/swizzle_table_format" ]]
+
+For more information on swizzling, see the Khronos wiki page
+<https://www.khronos.org/opengl/wiki/Data_Type_(GLSL)#Swizzling>
+
 ## Fail-on-First Mode <a name="ffirst-mode"></a>
 
 ffirst is a special data-dependent predicate mode.  There are two
diff --git a/simple_v_extension/vblock_format_table.mdwn b/simple_v_extension/vblock_format_table.mdwn
index d10a5e632..6698059c8 100644
--- a/simple_v_extension/vblock_format_table.mdwn
+++ b/simple_v_extension/vblock_format_table.mdwn
@@ -24,11 +24,11 @@ The VL/MAXVL/SubVL Block format, when 16xil != 0b111, is:
 """]]
 
 When 16xil is 0b111, this is the "Extended" Format, using the >= 192-bit
-RISC-V ISA format.  Note that the length is 80+16\*nnnnnn, not 192+
+RISC-V ISA format.  Note that the length is 96+16\*nnnnnn, not 192+
 
 | base+5 ... base+3         | base+1  | base             | no. of bits   |
 | ------ -----------------  |         | ---------------- | ------------- |
-| ..xxxx  xxxxxxxxxxxxxxxx  |         | x111xxxxx1111111 | 80+16\*nnnnnn |
+| ..xxxx  xxxxxxxxxxxxxxxx  |         | x111xxxxx1111111 | 96+16\*nnnnnn |
 | {ops}{Pred}{Reg}{VL Block}| VBLOCK2 | VBLOCK Prefix    |               |
 
 VBLOCK2 extends the VBLOCK fields: