From: Jan Kowalewski <jkowalewski@antmicro.com>
Date: Fri, 18 Oct 2019 07:33:31 +0000 (+0200)
Subject: cores/icap/ICAPBitstream: add source ready signal.
X-Git-Tag: 24jan2021_ls180~901^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8b5da9c62310cbc8fc84591ed50d1eaaf1df7a6a;p=litex.git

cores/icap/ICAPBitstream: add source ready signal.
---

diff --git a/litex/soc/cores/icap.py b/litex/soc/cores/icap.py
index 73319925..6c312dda 100644
--- a/litex/soc/cores/icap.py
+++ b/litex/soc/cores/icap.py
@@ -114,6 +114,7 @@ class ICAPBitstream(Module, AutoCSR):
         self.comb += [
             If(fifo.source.valid,
                 _csib.eq(0),
+                fifo.source.ready.eq(1),
                 _i.eq(fifo.source.data)
             )
         ]