From: Christoph Müllner Date: Tue, 28 Jun 2022 15:44:15 +0000 (+0200) Subject: RISC-V: Add support for arbitrary immediate encoding formats X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8b7419c429919884adced1fd2eae8c805b45b49a;p=binutils-gdb.git RISC-V: Add support for arbitrary immediate encoding formats This patch introduces support for arbitrary signed or unsigned immediate encoding formats. The formats have the form "XsN@S" and "XuN@S" with N being the number of bits and S the LSB position. For example an immediate field of 5 bytes that encodes a signed value and is stored in the bits 24-20 of the instruction word can use the format specifier "Xs5@20". Co-developed-by: Lifang Xia Signed-off-by: Christoph Müllner --- diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index 0a14b2cecc8..00e4635de6e 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -452,6 +452,9 @@ static char *expr_end; #define INSERT_OPERAND(FIELD, INSN, VALUE) \ INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD) +#define INSERT_IMM(n, s, INSN, VALUE) \ + INSERT_BITS ((INSN).insn_opcode, VALUE, (1ULL<X_add_number, n)) + as_bad (_("improper immediate value (%lu)"), + (unsigned long) imm_expr->X_add_number); + } + else + { + if (!VALIDATE_S_IMM (imm_expr->X_add_number, n)) + as_bad (_("improper immediate value (%li)"), + (long) imm_expr->X_add_number); + } + INSERT_IMM (n, s, *ip, imm_expr->X_add_number); + imm_expr->X_op = O_absent; + asarg = expr_end; + continue; + default: + goto unknown_riscv_ip_operand; + } + } + break; default: unknown_riscv_ip_operand: as_fatal (_("internal: unknown argument type `%s'"), diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index 6fdc9c9302e..faef28a3739 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -60,6 +60,7 @@ static const char * const riscv_pred_succ[16] = #define RV_X(x, s, n) (((x) >> (s)) & ((1 << (n)) - 1)) #define RV_IMM_SIGN(x) (-(((x) >> 31) & 1)) +#define RV_X_SIGNED(x, s, n) (RV_X(x, s, n) | ((-(RV_X(x, (s + n - 1), 1))) << (n))) #define EXTRACT_ITYPE_IMM(x) \ (RV_X(x, 20, 12) | (RV_IMM_SIGN(x) << 12)) @@ -347,6 +348,22 @@ static const char * const riscv_pred_succ[16] = #define EXTRACT_OPERAND(FIELD, INSN) \ EXTRACT_BITS ((INSN), OP_MASK_##FIELD, OP_SH_##FIELD) +/* Extract an unsigned immediate operand on position s with n bits. */ +#define EXTRACT_U_IMM(n, s, l) \ + RV_X (l, s, n) + +/* Extract an signed immediate operand on position s with n bits. */ +#define EXTRACT_S_IMM(n, s, l) \ + RV_X_SIGNED (l, s, n) + +/* Validate that unsigned n-bit immediate is within bounds. */ +#define VALIDATE_U_IMM(v, n) \ + ((unsigned long) v < (1UL << n)) + +/* Validate that signed n-bit immediate is within bounds. */ +#define VALIDATE_S_IMM(v, n) \ + (v < (long) (1UL << (n-1)) && v >= -(offsetT) (1UL << (n-1))) + /* The maximal number of subset can be required. */ #define MAX_SUBSET_NUM 4 diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c index 99cebf37d9e..2594e818254 100644 --- a/opcodes/riscv-dis.c +++ b/opcodes/riscv-dis.c @@ -562,7 +562,41 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info print (info->stream, dis_style_text, "%d", rs1); break; + case 'X': /* Integer immediate. */ + { + size_t n; + size_t s; + bool sign; + + switch (*++oparg) + { + case 's': /* 'XsN@S' ... N-bit signed immediate at bit S. */ + sign = true; + goto print_imm; + case 'u': /* 'XuN@S' ... N-bit unsigned immediate at bit S. */ + sign = false; + goto print_imm; + print_imm: + n = strtol (++oparg, (char **)&oparg, 10); + if (*oparg != '@') + goto undefined_modifier; + s = strtol (++oparg, (char **)&oparg, 10); + oparg--; + + if (!sign) + print (info->stream, dis_style_immediate, "%u", + (unsigned)EXTRACT_U_IMM (n, s, l)); + else + print (info->stream, dis_style_immediate, "%i", + (unsigned)EXTRACT_S_IMM (n, s, l)); + break; + default: + goto undefined_modifier; + } + } + break; default: + undefined_modifier: /* xgettext:c-format */ print (info->stream, dis_style_text, _("# internal error, undefined modifier (%c)"),