From: Udi Finkelstein <github@udifink.com>
Date: Wed, 6 Jun 2018 19:27:25 +0000 (+0300)
Subject: Detect illegal port declaration, e.g input/output/inout keyword must be the first.
X-Git-Tag: yosys-0.8~38^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8b7580b0a152ec937abb1510abf5f2d7cd3b7acb;p=yosys.git

Detect illegal port declaration, e.g input/output/inout keyword must be the first.
---

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index e803d8072..72a501d11 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -376,9 +376,10 @@ wire_type:
 	};
 
 wire_type_token_list:
-	wire_type_token | wire_type_token_list wire_type_token;
+	wire_type_token | wire_type_token_list wire_type_token |
+	wire_type_token_io ;
 
-wire_type_token:
+wire_type_token_io:
 	TOK_INPUT {
 		astbuf3->is_input = true;
 	} |
@@ -388,7 +389,9 @@ wire_type_token:
 	TOK_INOUT {
 		astbuf3->is_input = true;
 		astbuf3->is_output = true;
-	} |
+	};
+
+wire_type_token:
 	TOK_WIRE {
 	} |
 	TOK_REG {