From: lkcl Date: Tue, 22 Dec 2020 23:25:52 +0000 (+0000) Subject: (no commit message) X-Git-Tag: convert-csv-opcode-to-binary~1026 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8b935f76d985a0dad03a1496f481cb4727b94e3e;p=libreriscv.git --- diff --git a/openpower/sv/vector_ops.mdwn b/openpower/sv/vector_ops.mdwn index b23e92548..736583675 100644 --- a/openpower/sv/vector_ops.mdwn +++ b/openpower/sv/vector_ops.mdwn @@ -1,6 +1,6 @@ # SV Vector Operations. -The core OpenPOWER ISA was designed as scalar: SV provides a level of abstraction to add variable-length element-independent parallelism. However, certain classes of instructions only make sense in a Vector context: AVC512 conflictd for example. This section includes such examples. Many of them are from the RISC-V Vector ISA (with thanks to the efforts of RVV's contributors) +The core OpenPOWER ISA was designed as scalar: SV provides a level of abstraction to add variable-length element-independent parallelism. However, certain classes of instructions only make sense in a Vector context: AVX512 conflictd for example. This section includes such examples. Many of them are from the RISC-V Vector ISA (with thanks to the efforts of RVV's contributors) However some of these actually could be added to a scalar ISA as bitmanipulation instructions. These are separated out into their own section. Instructions suited to 3D GPU workloads (dotproduct, crossproduct, normalise) are out of scope: this document is for more general-purpose instructions that underpin and are critical to general-purpose Vector workloads (including GPU and VPU)