From: Aman Goel <amangoel@umich.edu>
Date: Mon, 14 May 2018 22:58:49 +0000 (-0400)
Subject: Minor correction
X-Git-Tag: yosys-0.8~10^2~6
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8b9a8c7f9115e691dc832b3be3d82b55be507e99;p=yosys.git

Minor correction

Minor typo error correction in -expose with setundef
---

diff --git a/passes/cmds/setundef.cc b/passes/cmds/setundef.cc
index 0825cf83e..9b0c30cae 100644
--- a/passes/cmds/setundef.cc
+++ b/passes/cmds/setundef.cc
@@ -89,7 +89,6 @@ static RTLIL::Wire * add_wire(RTLIL::Design *design, RTLIL::Module *module, std:
   return wire;
 }
 
-
 struct SetundefWorker
 {
 	int next_bit_mode;
@@ -304,7 +303,7 @@ struct SetundefPass : public Pass {
             else {
               string name = c.wire->name.str() + "$[" + std::to_string(c.width + c.offset) + ":" + std::to_string(c.offset) + "]";
               wire = add_wire(design, module, name, c.width, true, false, false);
-              module->connect(RTLIL::SigSig(c.wire, wire));
+              module->connect(RTLIL::SigSig(c, wire));
             }
             log("Exposing undriven wire %s as input.\n", wire->name.c_str());
           }