From: Jacob Lifshay <programmerjake@gmail.com>
Date: Wed, 24 Aug 2022 11:31:43 +0000 (-0700)
Subject: misc cleanup
X-Git-Tag: sv_maxu_works-initial~123
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8b9d7f986fa0977dfe68193eab7c1632d59cb420;p=openpower-isa.git

misc cleanup
---

diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py
index e3540d0d..a7d626fc 100644
--- a/src/openpower/decoder/isa/caller.py
+++ b/src/openpower/decoder/isa/caller.py
@@ -1263,7 +1263,7 @@ class ISACaller(ISACallerHelper, ISAFPHelpers):
 
         # nop has to be supported, we could let the actual op calculate
         # but PowerDecoder has a pattern for nop
-        if ins_name is 'nop':
+        if ins_name == 'nop':
             self.update_pc_next()
             return
 
@@ -1332,9 +1332,9 @@ class ISACaller(ISACallerHelper, ISAFPHelpers):
         # main input registers (RT, RA ...)
         inputs = []
         for name in input_names:
-            print("name", name)
+            log("name", name)
             regval = (yield from self.get_input(name))
-            print("regval", regval)
+            log("regval", regval)
             inputs.append(regval)
 
         # arrrrgh, awful hack, to get _RT into namespace
@@ -1663,7 +1663,7 @@ class ISACaller(ISACallerHelper, ISAFPHelpers):
                     shape_idx = self.svstate_next_mode.value-1
                     endings = self.remap_loopends[shape_idx]
                 cr_field = SelectableInt((~endings) << 1 | endtest, 4)
-                print("svstep Rc=1, CR0", cr_field)
+                log("svstep Rc=1, CR0", cr_field)
                 self.crl[0].eq(cr_field)  # CR0
             if end_src or end_dst:
                 # reset at end of loop including exit Vertical Mode