From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 14 Apr 2020 19:35:12 +0000 (-0700)
Subject: abc9_ops: -prep_dff_map to check $_DFF_[NP]_.Q drives module output
X-Git-Tag: working-ls180~549^2~47
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8bad885e782181837c710f738f6184bd473d88ae;p=yosys.git

abc9_ops: -prep_dff_map to check $_DFF_[NP]_.Q drives module output
---

diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc
index d15da348a..2f1b531e2 100644
--- a/passes/techmap/abc9_ops.cc
+++ b/passes/techmap/abc9_ops.cc
@@ -175,6 +175,10 @@ void prep_dff_map(RTLIL::Design *design)
 				//   because ABC9 doesn't support them
 				Q = cell->getPort(ID::Q);
 				log_assert(GetSize(Q.wire) == 1);
+
+				if (!Q.wire->port_output)
+					log_error("Module '%s' contains a %s cell where its 'Q' port does not drive a module output!\n", log_id(module), log_id(cell->type));
+
 				Const init = Q.wire->attributes.at(ID::init, State::Sx);
 				log_assert(GetSize(init) == 1);
 				if (init != State::S0) {
@@ -1207,7 +1211,7 @@ struct Abc9OpsPass : public Pass {
 		log("    -prep_dff_unmap\n");
 		log("        fill in previously created '$abc9_unmap' design to contain techmap rules\n");
 		log("        for mapping *_$abc9_flop cells back into their original (* abc9_flop *)\n");
-		log("         cells(including their original parameters).\n");
+		log("        cells (including their original parameters).\n");
 		log("\n");
 		log("    -prep_delays\n");
 		log("        insert `$__ABC9_DELAY' blackbox cells into the design to account for\n");